View MC9S12H128_182884.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor, Inc.
DOCUMENT NUMBER 9S12H256BDGV1/D
MC9S12H256 Device User Guide V01.18 Covers also MC9S12H128
Freescale Semiconductor, Inc...
Original Release Date: 29 SEP 2000 Revised: 13 AUG 2003
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
1 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
DOCUMENT NUMBER 9S12H256BDGV1/D
Revision History
Version Revision Effective Number Date Date
V01.00 V01.01 07 MAR 2001 10 MAI 2001 14 MAY 2001 30 MAY 2001 11 JUN 2001 18 JUN 2001 03 APR 2001 10 MAY 2001 14 MAY 2001 30 MAY 2001 11 JUN 2001 18 JUN 2001
Author
Initial version.
Description of Changes
- Minor formal corrections - Changed ATD coupling ratio to10-2 - Changed VDD5 to 4.5V - Removed 112-pin package references - Changed ATD Electrical Characteristics separate coupling ratio for positive and negative bulk current injection - Reinserted 112-pin package information. - Removed SRSv2 comment from preface - Corrected RESET pin to active low in table 2-1 - Adapted style and wording to 9DP256 device user guide - Minor format and wording improvements - Added SRAM data retention disclaimer - Changed Oscillator Characteristics tCQOUT max 2.5s and replaced Clock Monitor Time-out by Clock Monitor Failure Assert Frequency - Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz - Changed IDDPS (RTI and COP disabled) to 400A - Corrected typo in Figure 2-1 pin 76: PK3 -> PK2 - Added tEXTR and tEXTF to Oscillator Characteristics - Added typ value for tUPOSC - Corrected tEXTL and tEXTH values - Updated thermal resistances as per Thermal Simulation Report, July 10, 2001 - updated EEPROM size - added DC cutoff capacitor into layout proposals - minor updates - updated electrical spec
Freescale Semiconductor, Inc...
V01.02 V01.03 V01.04 V01.05
V01.06
28 JUN 2001
28 JUN 2001
V01.07
12 JUL 2001 16 JUL 2001 03 AUG 2001 29 AUG 2001
12 JUL 2001 16 JUL 2001 03 AUG 2001 29 AUG 2001
V01.08 V01.09 V01.10
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
2 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Version Revision Effective Number Date Date
V01.11 V01.12 11 OCT 2001 07 NOV 2001 11 OCT 2001 07 NOV 2001
Author
Description of Changes
- Replaced references w.r.t. new family name HCS12. - Corrected XCLKS reference in CRG electrical spec. - added `powered by' column in pin list table - new document numbering - removed document order number except from cover sheet - updated min VDD, VDDPLL - updated currents on VOH,VOL for standard pins - updated CIN, IDDS, IREF, CINS, TEXTL, TEXTH - included missing lcd electrical spec - updated NVM spec - updated input leakage - updated slew rate spec on PU,PV, PW - updated supply currents - included 1K78X - added detailed register map - added K1 max value - added chragepump current min/max values - corrected pinout problem in LQFP112 layout proposal - added MC9S12H128 - added Internal Pull Resistor columns to signal properties table
V01.13
08 MAR 2002
08 MAR 2002
Freescale Semiconductor, Inc...
V01.14
16 DEC 2002 31 MAR 2003 05 NOV 2003 04 AUG 2004 13 AUG 2004
16 DEC 2002 31 MAR 2003 05 NOV 2003 04 AUG 2004 13 AUG 2004
V01.15 V01.16 V01.17 V01.18
3 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
4 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.2 Signal Properties Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.4 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin. . . . . . . . . . . . . 60 2.3.6 PAD[15:8] / AN[15:8] -- Port AD Input Pins [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.7 PAD[7:0] / AN[7:0] -- Port AD Input Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . 60 2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 61 2.3.10 PE7 / FP22 / XCLKS / NOACC -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.11 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.12 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.13 PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.14 PE3 / FP21 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.15 PE2 / FP20 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.16 PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.17 PE0 / XIRQ -- Port E Input Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.18 PH[7:0] / KWH[7:0] -- Port H I/O Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.19 PJ[3:0] / KWJ[3:0] -- Port J I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.20 PK7 / FP23 / ECS / ROMONE -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] -- Port K I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.22 PL[7:4] / FP[31:28] -- Port L I/O Pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.23 PL[3:0] / FP[19:16] -- Port L I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Freescale Semiconductor, Inc...
5 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
2.3.24 PM5 / TXCAN1 -- Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.25 PM4 / RXCAN1 -- Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.26 PM3 / TXCAN0 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.27 PM2 / RXCAN0 -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.28 PM1 / SCL -- Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.29 PM0 / SDA -- Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.30 PP[5:2] / PWM[5:2] -- Port P I/O Pins [5:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.31 PP[1:0] / PWM[1:0] -- Port P I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.32 PS7 / SS -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.33 PS6 / SCK -- Port S I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.34 PS5 / MOSI -- Port S I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.35 PS4 / MISO -- Port S I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.36 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.37 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.38 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.39 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.40 PT[7:4] / IOC[7:4] -- Port T I/O Pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.41 PT[3:0] / IOC[3:0] / FP[27:24] -- Port T I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.42 PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M -- Port U I/O Pins [7:4] . . . . . . . . . . . . . . . . 65 2.3.43 PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M -- Port U I/O Pins [3:0] . . . . . . . . . . . . . . . . 65 2.3.44 PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M -- Port V I/O Pins [7:4] . . . . . . . . . . . . . . . . 65 2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M -- Port V I/O Pins [3:0] . . . . . . . . . . . . . . . . 66 2.3.46 PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M -- Port W I/O Pins [7:4] . . . . . . . . . . . . . . . 66 2.3.47 PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M -- Port W I/O Pins [3:0] . . . . . . . . . . . . . . . 66 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.1 VDDR -- External Power Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.2 VDDX1, VDDX2, VSSX1, VSSX2 -- External Power and Ground Pins . . . . . . . . . . . . . . . 66 2.4.3 VDD1, VSS1, VSS2 -- Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.5 VDDM1, VDDM2, VDDM3 -- Power Supply Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . 67 2.4.6 VSSM1, VSSM2, VSSM3 -- Ground Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.7 VLCD -- Power Supply Reference Pin for LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.8 VRH, VRL -- ATD Reference Voltage Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.9 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Freescale Semiconductor, Inc...
Section 3 System Clock Description
6 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Section 4 Modes of Operation
4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Normal Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Test Operating Mode (Motorola Use Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Freescale Semiconductor, Inc...
Section 5 Resets and Interrupts
5.1 5.2 5.2.1 5.3 5.3.1 5.3.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Section 6 HCS12 Core Block Description Section 7 Clock and Reset Generator (CRG) Block Description
7.1 7.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 XCLKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Section 8 Timer (TIM) Block Description Section 9 Analog to Digital Converter (ATD) Block Description Section 10 Inter-IC Bus (IIC) Block Description Section 11 Serial Communications Interface (SCI) Block Description Section 12 Serial Peripheral Interface (SPI) Block Description
7 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Section 13 Pulse Width Modulator (PWM) Block Description Section 14 Flash EEPROM 256K Block Description Section 15 EEPROM 4K Block Description Section 16 RAM Block Description Section 17 Liquid Crystal Display Driver (LCD) Block Description Section 18 MSCAN Block Description
Freescale Semiconductor, Inc...
Section 19 PWM Motor Control (MC) Block Description Section 20 Port Integration Module (PIM) Block Description Section 21 Voltage Regulator (VREG) Block Description
21.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21.1.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21.2 Recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Appendix A Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A.1.3 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.2.3 A.3 A.3.1 A.3.2 A.4 A.4.1 A.4.2 A.4.3 A.5 A.6 A.6.1 A.6.2 A.7 A.8 A.8.1 ATD accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 NVM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LCD_32F4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 General Muxed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Freescale Semiconductor, Inc...
Appendix B Package Information
B.1 B.2 B.3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 112-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 144-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
10 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 2-1 Figure 2-2 Figure 3-1 Figure 21-1 Figure 21-2 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure B-1 Figure B-2 MC9S12H256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MC9S12H128 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MC9S12H256 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MC9S12H128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128 . . . . . . . . . . 56 Pin Assignments in 144-pin LQFP for MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . 57 Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LQFP112 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LQFP144 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Slave Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 General External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . . . . . . 126 144-pin LQFP mechanical dimensions (case no. 918-03) . . . . . . . . . . . . . . . . . . . . . 127
Freescale Semiconductor, Inc...
11 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
12 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Table 0-1 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 1-1 Device Memory Map MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 1-2 Device Memory Map MC9S12H128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 44 Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 46 Table 1-5 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 1-6 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 5-1 Reset and Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 21-1 Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table A-2 ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table A-13 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table A-14 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table A-15 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table A-16 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table A-17 SPI Master Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table A-18 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LCD_32F4B Driver Electrical Characteristics 119 Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Freescale Semiconductor, Inc...
13 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
14 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Preface
The Device User Guide provides information about the MC9S12H256 and MC9S12H128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In an effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
Freescale Semiconductor, Inc...
Table 0-1 Document References
User Guide
HCS12 V1.5 Core User Guide CRG Block User Guide TIM_16B8C Block User Guide ATD_10B16C Block User Guide IIC Block User Guide SCI Block User Guide SPI Block User Guide PWM_8B6C Block User Guide FTS256K Block User Guide EETS4K Block User Guide LCD_32F4B Block User Guide MSCAN Block User Guide MC_10B12C Block User Guide PIM_9H256 Block User Guide VREG Block User Guide
Version
1.2 V02 V01 V02 V02 V02 V02 V01 V02 V02 V01 V02 V02 V01 V01
Document Order Number
HCS12COREUG S12CRGV2/D S12TIM16B8CV1/D S12ATD10B16CV2/D S12IICV2/D S12SCIV2/D S12SPIV2/D S12PWM8B6CV1/D S12FTS256KV2/D S12EETS4KV2/D S12LCD32F4BV1/D S12MSCANV2/D S12MC10B12CV2/D S12PIMH256V1/D S12VREGV1/D
15 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
16 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Section 1 Introduction
1.1 Overview
The MC9S12H256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B software compatible modules (MSCAN). The MC9S12H128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 6K bytes of RAM, 2K bytes of EEPROM, one asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 8-channel, 10-bit analog-to-digital converter (ATD), a two-channel pulse width modulator (PWM), and two CAN 2.0 A, B software compatible modules (MSCAN). In addition, it features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of 24 high current outputs suited to drive up to 6 stepper motors. System resource mapping, clock generation, interrupt control, and bus interfacing are managed by the HCS12 Core. The MC9S12H256 has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 12 general purpose I/O pins are available with interrupt and wake-up capability from STOP or WAIT mode.
Freescale Semiconductor, Inc...
1.2 Features
* HCS12 Core - 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. 20-bit ALU iv. Instruction queue v. Enhanced indexed addressing - - - - MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) INT (Interrupt control) BKP (Breakpoints)
17 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
- * * BDM (Background Debug Mode)
Semiconductor, Inc.
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) 8-bit and 4-bit ports with interrupt functionality - - Digital filtering Programmable rising or falling edge trigger 128K, 256K Flash EEPROM 2K, 4K byte EEPROM 6K, 12K byte RAM 8, 16 channels, 10-bit resolution External conversion trigger capability Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function Loop-back for self test operation 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators Programmable period and duty cycle 8-bit 2, 6-channel or 16-bit 1, 3-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Two asynchronous Serial Communications Interfaces (SCI) Synchronous Serial Peripheral Interface (SPI)
*
Memory - - -
*
Analog-to-Digital Converter - -
Freescale Semiconductor, Inc...
*
Two 1M bit per second, CAN 2.0 A, B software compatible modules - - - - -
*
Timer - - -
*
2, 6 PWM channels - - - - - -
*
Serial interfaces - -
18 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
- * - - - * - - - - Inter-Integrated Circuit interface (IIC) Configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output 5 modes of operation allow for different display sizes to meet application requirements Unused frontplane and backplane pins can be used as general purpose I/O Each PWM channel switchable between two drivers in an H-bridge configuration Left, right and center aligned outputs Support for sine and cosine drive Dithering Output slew rate control I/O lines with 5V input and drive capability 5V A/D converter inputs Operation at 32MHz equivalent to 16MHz Bus Speed Development support Single-wire background debugTM mode (BDM) On-chip hardware breakpoints
Liquid Crystal Display driver with variable input voltage
16, 24 high current drivers suited for PWM motor control
Freescale Semiconductor, Inc...
- * - - - - - -
144-Pin or 112-Pin LQFP package
1.3 Modes of Operation
User modes * Normal and Emulation Operating Modes - - - - - * - - - Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola Use Only) Special Peripheral Mode (Motorola Use Only)
Special Operating Modes
Low power modes
19 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
* * * Stop Mode Pseudo Stop Mode Wait Mode
Semiconductor, Inc.
1.4 Block Diagram
Figure 1-1 is a block diagram of the MC9S12H256 device.
Freescale Semiconductor, Inc...
20 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
VDDR VDD1 VSS1,VSS2 Voltage Regulator VDDA VSSA VRH VRL AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 PW0 PW1 PW2 PW3 PW4 PW5 RXD0 TXD0 VDDA VSSA VRH VRL PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PP0 PP1 PP2 PP3 PP4 PP5 PS0 PS1
256k Bytes Flash EEPROM 4k Bytes EEPROM 12K Bytes RAM BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE4 PE5 PE6 XIRQ IRQ ECLK MODA MODB VLCD BP0 BP1 BP2 BP3 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 IOC4 IOC5 IOC6 IOC7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 KWJ0 KWJ1 KWJ2 KWJ3 R/W LSTRB/TAGLO NOACC/XCLKS ECS/ROMONE IOC0 IOC1 IOC2 IOC3 Input Capture and Output Compare Timer PIX0 PIX1 PIX2 PIX3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 Single-wire Background Debug Module Clock and Reset Generation Module CPU12 Periodic Interrupt COP Watchdog Clock Monitor Breakpoints Analog to Digital Converter (ATD)
PLL
DDRE
PTE
DDRP
Integration Module
Pulse Width Modulator (PWM)
PTAD PTP
Freescale Semiconductor, Inc...
VLCD XADDR14 XADDR15 XADDR16 XADDR17 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Multiplexed Narrow Bus DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Multiplexed Wide Bus PK0 PK1 PK2 PK3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE2 PE3 PE7 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PJ0 PJ1 PJ2 PJ3
PPAGE
SCI0 SCI1
DDRK
PTK
DDRS
PTS
RXD1 TXD1 SDI/MISO SDO/MOSI SCK SS SDA SCL
PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1
SPI
LCD Driver
Multiplexed Address/Data Bus
DDRB
PTB
IIC CAN0 CAN1
RXCAN1 TXCAN1
PTM
RXCAN0 TXCAN0
DDRM
PM2 PM3 PM4 PM5 VDDM1
DDRA
PTA
MOTOR0 and MOTOR1 Supply PWM0 MOTOR0 PWM1 PWM2 MOTOR1 PWM3
M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P
VSSM1 PU0 PU1
DDRU
PTU
PU2 PU3 PU4 PU5 PU6 PU7 VDDM2 VSSM2 PV0 PV1
DDRL
PTL
MOTOR2 and MOTOR3 Supply PWM4 MOTOR2 PWM5 PWM6 MOTOR3 PWM7
NOTE: Not all functionality shown in this block diagram is available in all packages!
M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P
DDRE
PTE
DDRV
DDRK
PTV
PV2 PV3 PV4 PV5 PV6 PV7 VDDM3 VSSM3 PW0 PW1 PW2 PW3 PW4 PW5 PW6 PW7
PTK
DDRT
MOTOR4 and MOTOR5 Supply PWM8 MOTOR4 PWM9 PWM10 MOTOR5 PWM11 Supply pins
PTT
DDRH
M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
DDRW
PTH
Pin Interrupt Logic
A/D Converter 5V & Voltage Regulator Reference VDDA VSSA
Internal Logic 2.5V I/O Driver 5V VDD1 VDDX1,2 VSS1,2 VSSX1,2 PLL 2.5V VDDPLL VSSPLL
DDRJ
VREG Input 5V VDDR
PTJ
Figure 1-1 MC9S12H256 Block Diagram
PTW
21 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Figure 1-2 is a block diagram of the MC9S12H128 device.
Freescale Semiconductor, Inc...
22 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
VDDR VDD1 VSS1,VSS2 Voltage Regulator VDDA VSSA VRH VRL AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 VDDA VSSA VRH VRL PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
128k Bytes Flash EEPROM 2k Bytes EEPROM 6K Bytes RAM BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE4 PE5 PE6 XIRQ IRQ ECLK MODA MODB VLCD BP0 BP1 BP2 BP3 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 PIX0 PIX1 PIX2 PIX3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 Single-wire Background Debug Module Clock and Reset Generation Module CPU12 Periodic Interrupt COP Watchdog Clock Monitor Breakpoints Analog to Digital Converter (ATD)
PLL
PTAD
DDRE
PTE
DDRP
Integration Module
Pulse Width Modulator (PWM)
PW0 PW1 PW2 PW3 PW4 PW5 RXD0 TXD0
PP0 PP1 PP2 PP3 PP4 PP5 PS0 PS1
Freescale Semiconductor, Inc...
VLCD XADDR14 XADDR15 XADDR16 XADDR17 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Multiplexed Narrow Bus DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Multiplexed Wide Bus PK0 PK1 PK2 PK3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PL0 PL1 PL2 PL3
PPAGE
SCI0
DDRK
PTK
DDRS
PTS
PTP
SPI
LCD Driver
Multiplexed Address/Data Bus
DDRB
SDI/MISO SDO/MOSI SCK SS SDA SCL
PS4 PS5 PS6 PS7 PM0 PM1
PTB
IIC CAN0 CAN1
RXCAN1 TXCAN1
PTM
RXCAN0 TXCAN0
DDRM
PM2 PM3 PM4 PM5 VDDM1
DDRA
PTA
MOTOR0 and MOTOR1 Supply PWM0 MOTOR0 PWM1 PWM2 MOTOR1 PWM3
M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P
VSSM1 PU0 PU1
DDRU
PTU
PU2 PU3 PU4 PU5 PU6 PU7 VDDM2 VSSM2 PV0 PV1
DDRL
PTL
MOTOR2 and MOTOR3 Supply PE2 PE3 PE7 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 IOC4 IOC5 IOC6 IOC7 R/W LSTRB/TAGLO NOACC/XCLKS ECS/ROMONE IOC0 IOC1 IOC2 IOC3 Input Capture and Output Compare Timer
PTE
PWM4 MOTOR2 PWM5 PWM6 MOTOR3 PWM7
NOTE: Not all functionality shown in this block diagram is available in all packages!
M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P
DDRE
DDRV
DDRK
PTV
PV2 PV3 PV4 PV5 PV6 PV7 VDDM3 VSSM3 PW0 PW1 PW2 PW3 PW4 PW5 PW6 PW7
PTK
DDRT
MOTOR4 and MOTOR5 Supply PWM8 MOTOR4 PWM9 PWM10 MOTOR5 PWM11 Supply pins A/D Converter 5V & Voltage Regulator Reference VDDA VSSA
PTT
M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
DDRW
Internal Logic 2.5V I/O Driver 5V VDD1 VDDX1,2 VSS1,2 VSSX1,2 PLL 2.5V VDDPLL VSSPLL
VREG Input 5V VDDR
Figure 1-2 MC9S12H128 Block Diagram
PTW
23 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
1.5 Device Memory Map
Freescale Semiconductor, Inc...
24 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Freescale Semiconductor, Inc...
25 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table 1-1 and Figure 1-3 show the device memory map of the MC9S12H256. Table 1-1 Device Memory Map MC9S12H256
Address
$0000 - $0017 $0018 - $0019 $001A - $001B $001C - $001F $0020 - $0027 $0028 - $002F $0030 - $0033 $0034 - $003F $0040 - $006F Reserved Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) Reserved CORE (Background Debug Mode) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Standard Timer Module 16-bit 8 channels (TIM) Reserved Analog to Digital Converter 10-bit 16 channels (ATD) Reserved Inter Integrated Circuit (IIC) Serial Communications Interface 0 (SCI0) Serial Communications Interface 1 (SCI1) Serial Peripheral Interface (SPI) Pulse Width Modulator 8-bit 6 channels (PWM) Flash control registers EEPROM control registers Reserved Liquid Crystal Display Driver 32x4 (LCD) Motorola Scalable Controller Area Network 0 (MSCAN0) Motorola Scalable Controller Area Network 1 (MSCAN1) Motor Control Module (MC) Port Integration Module (PIM) Reserved EEPROM array RAM array Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at start Flash EEPROM Page Window Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size (Bytes)
24 2 2 4 8 8 4 12 48 16 48 16 8 8 8 8 32 16 12 4 24 64 64 64 128 384 4096 12288 16384 16384 16384
Freescale Semiconductor, Inc...
$0070 - $007F $0080 - $00AF $00B0 - $00BF $00C0 - $00C7 $00C8 - $00CF $00D0 - $00D7 $00D8 - $00DF $00E0 - $00FF $0100 - $010F $0110 - $011B $011C - $011F $0120 - $0137 $0140 - $017F $0180 - $01BF $01C0 - $01FF $0200 - $027F $0280 - $03FF $0000 - $0FFF $1000 - $3FFF $4000 - $7FFF $8000 - $BFFF $C000 - $FFFF
26 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0000 $0000 $0400 $0800 $1000 $03FF $0000 $0FFF $1000 1K Register Space Mappable to any 2K Boundary 4K Bytes EEPROM initially overlapped by register space Mappable to any 4K Boundary 12K Bytes RAM Alignable to top ($1000 - $3FFF) or bottom ($0000 - $2FFF) $4000 $3FFF $4000 Mappable to any 16K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF $8000
16K Fixed Flash EEPROM
Freescale Semiconductor, Inc...
$8000 EXT $BFFF $C000 $C000
16K Page Window Sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED* VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
* Assuming that a `0' was driven onto port K7 during reset to normal expanded mode
Figure 1-3 MC9S12H256 Memory Map Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128. Table 1-2 Device Memory Map MC9S12H128
Address
$0000 - $0017 $0018 - $0019 $001A - $001B $001C - $001F $0020 - $0027 $0028 - $002F $0030 - $0033 $0034 - $003F $0040 - $006F $0070 - $007F $0080 - $00AF $00B0 - $00BF $00C0 - $00C7 Reserved Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) Reserved CORE (Background Debug Mode) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Standard Timer Module 16-bit 8 channels (TIM) Reserved Analog to Digital Converter 10-bit 16 channels (ATD) Reserved Inter Integrated Circuit (IIC)
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size (Bytes)
24 2 2 4 8 8 4 12 48 16 48 16 8
27 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table 1-2 Device Memory Map MC9S12H128
Address
$00C8 - $00CF $00D0 - $00D7 $00D8 - $00DF $00E0 - $00FF $0100 - $010F $0110 - $011B $011C - $011F $0120 - $0137 $0140 - $017F $0180 - $01BF $01C0 - $01FF $0200 - $027F $0280 - $03FF $0000 - $07FF $1000 - $3FFF $4000 - $7FFF $8000 - $BFFF $C000 - $FFFF Reserved Serial Peripheral Interface (SPI) Pulse Width Modulator 8-bit 6 channels (PWM) Flash control registers EEPROM control registers Reserved Liquid Crystal Display Driver 32x4 (LCD) Motorola Scalable Controller Area Network 0 (MSCAN0) Motorola Scalable Controller Area Network 1 (MSCAN1) Motor Control Module (MC) Port Integration Module (PIM) Reserved EEPROM array RAM array Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at start Flash EEPROM Page Window Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF
Module
Serial Communications Interface 0 (SCI0)
Size (Bytes)
8 8 8 32 16 12 4 24 64 64 64 128 384 2048 12288 16384 16384 16384
Freescale Semiconductor, Inc...
28
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0000 $0000 $0400 $0800 $2800 $03FF $0000 $07FF $2800 1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM initially overlapped by register space Mappable to any 4K Boundary 6K Bytes RAM Alignable to top ($2800 - $3FFF) or bottom ($0000 - $17FF) $3FFF $4000 Mappable to any 16K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF $8000
16K Fixed Flash EEPROM
Freescale Semiconductor, Inc...
$8000 EXT $BFFF $C000 $C000
16K Page Window Sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED* VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
* Assuming that a `0' was driven onto port K7 during reset to normal expanded mode
Figure 1-4 MC9S12H128 Memory Map
29 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18 1.5.1 Detailed Register Map
$0000 - $000F
Address $0000 $0001 $0002 $0003 $0004 Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
Semiconductor, Inc.
MEBI map 1 of 3 (Core User Guide)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 Bit 3 3 3 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 EME PUPAE RDPA ESTR 0
Freescale Semiconductor, Inc...
$0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
$0010 - $0014
Address $0010 $0011 $0012 $0013 $0014 Name INITRM INITRG INITEE MISC MTST0 Test Only
MMC map 1 of 4 (Core User Guide)
Bit 7 Read: RAM15 Write: Read: 0 Write: Read: EE15 Write: Read: 0 Write: Read: Bit 7 Write: Bit 6 RAM14 REG14 EE14 0 6 Bit 5 RAM13 REG13 EE13 0 5 Bit 4 RAM12 REG12 EE12 0 4 Bit 3 RAM11 REG11 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 RAMHAL 0 EEON
EXSTR1 EXSTR0 ROMHM ROMON 3 2 1 Bit 0
30 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0015 - $0016
Address $0015 $0016 Name ITCR ITEST Read: Write: Read: Write:
INT map 1 of 2 (Core User Guide)
Bit 7 0 INTE Bit 6 0 INTC Bit 5 0 INTA Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0
$0017 - $0017
Address $0017 Name MTST1 Test Only Read: Write:
MMC map 2 of 4 (Core User Guide)
Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0
Freescale Semiconductor, Inc...
$0018 - $001B
Address $0018 $0019 $001A $001B Name Reserved Reserved PARTIDH PARTIDL Read: Write: Read: Write: Read: Write: Read: Write:
Miscellaneous Peripherals (Device User Guide, Table 1-5)
Bit 7 0 0 ID15 ID7 Bit 6 0 0 ID14 ID6 Bit 5 0 0 ID13 ID5 Bit 4 0 0 ID12 ID4 Bit 3 0 0 ID11 ID3 Bit 2 0 0 ID10 ID2 Bit 1 0 0 ID9 ID1 Bit 0 0 0 ID8 ID0
$001C - $001D
Address $001C $001D Name MEMSIZ0 MEMSIZ1
MMC map 3 of 4 (Core and Device User Guide, Table 1-6)
Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0
$001E - $001E
Address $001E Name INTCR Read: Write:
MEBI map 2 of 3 (Core User Guide)
Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$001F - $001F
Address $001F Name HPRIO Read: Write:
INT map 2 of 2 (Core User Guide)
Bit 7 PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0
31 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0020 - $0027
Address $0020 $0027 Name Reserved Read: Write:
Semiconductor, Inc.
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0028 - $002F
Address $0028 $0029 $002A Name BKPCT0 BKPCT1 BKP0X BKP0H BKP0L BKP1X BKP1H BKP1L
BKP (Core User Guide)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write:
Freescale Semiconductor, Inc...
$002B $002C $002D $002E $002F
$0030 - $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
MMC map 4 of 4 (Core User Guide)
Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
$0032 - $0033
Address $0032 $0033 Name PORTK DDRK Read: Write: Read: Write:
MEBI map 3 of 3 (Core User Guide)
Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0
32 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
CRG (Clock and Reset Generator)
Bit 7 Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: 0 Write: Read: WCOP Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 7 Bit 6 0 0 0 PORF 0 PSTP PLLON RTR6 RSBCK 0 0 0 6 Bit 5 SYN5 0 0 0 0 Bit 4 SYN4 0 0 LOCKIF LOCKIE Bit 3 SYN3 Bit 2 SYN2 Bit 1 SYN1 Bit 0 SYN0
REFDV3 REFDV2 REFDV1 REFDV0 0 LOCK 0 PLLWAI 0 RTR3 0 0 0 0 3 0 TRACK 0 CWAI PRE RTR2 CR2 0 0 0 2 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1 0 SCM 0 COPWAI SCME RTR0 CR0 0 0 0 Bit 0
SYSWAI ROAWAI AUTO RTR5 0 0 0 0 5 ACQ RTR4 0 0 0 0 4
Freescale Semiconductor, Inc...
$003A $003B $003C $003D $003E $003F
$0040 - $006F
Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2
TIM (Timer 16 Bit 8 Channels)
Bit 7 Read: IOS7 Write: Read: 0 Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: TEN Write: Read: TOV7 Write: Read: OM7 Write: Read: OM3 Write: Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 TSWAI TOV6 OL7 OL3 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 TFFCA TOV4 OL6 OL2 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 0 TOV3 OM5 OM1 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 TOV2 OL5 OL1 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 TOV1 OM4 OM0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TOV0 OL4 OL0
33 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0040 - $006F
Address $004A $004B $004C $004D $004E $004F Name TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACNT (hi)
Semiconductor, Inc.
TIM (Timer 16 Bit 8 Channels)
Bit 7 Read: EDG7B Write: Read: EDG3B Write: Read: C7I Write: Read: TOI Write: Read: C7F Write: Read: TOF Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Bit 6 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 PAEN 0 6 Bit 5 EDG6B EDG2B C5I 0 C5F 0 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 PAMOD 0 5 Bit 4 EDG6A EDG2A C4I 0 C4F 0 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 PEDGE 0 4 Bit 3 EDG5B EDG1B C3I TCRE C3F 0 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 CLK1 0 3 Bit 2 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 CLK0 0 2 Bit 1 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 PAOVI PAOVF 1 Bit 0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0
Freescale Semiconductor, Inc...
$0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 $0062
34 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0040 - $006F
Address $0063 $0064 $0065 $0066 $0067 $0068 Name PACNT (lo) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMTST Test Only Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
TIM (Timer 16 Bit 8 Channels)
Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0
Freescale Semiconductor, Inc...
$0069 $006A $006B $006C $006D $006E $006F
0
0
0
0
0
0
TCBYP
PCBYP
$0070 - $007F
Address $0070 $007F Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0080 - $00AF
Address $0080 $0081 $0082 $0083 $0084 $0085 Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Bit 6 0 0 AFFC S8C SMP1 DSGN Bit 5 0 0 AWAI S4C SMP0 SCAN Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC Bit 1 0 0 ASCIE FRZ1 PRS1 CB Bit 0 0 0 ASCIF FRZ0 PRS0 CA
ETRIGLE ETRIGP S2C PRS4 MULT S1C PRS3 CD
35 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0080 - $00AF
Address $0086 $0087 $0088 $0089 $008A $008B Name ATDSTAT0 Reserved ATDTEST0 ATDTEST1 ATDSTAT2 ATDSTAT1 ATDDIEN0 ATDDIEN1 PORTAD0 PORTAD1 ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 SCF 0 SAR9 SAR1 CCF15 CCF7 Bit 15 Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit 6 0 0 SAR8 SAR0 CCF14 CCF6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 Bit 5 ETORF 0 SAR7 0 CCF13 CCF5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 Bit 4 FIFOR 0 SAR6 0 CCF12 CCF4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 Bit 3 CC3 0 SAR5 0 CCF11 CCF3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 Bit 2 CC2 0 SAR4 RST CCF10 CCF2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 Bit 1 CC1 0 SAR3 ATDCLK CCF9 CCF1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 Bit 0 CC0 0 SAR2 SC CCF8 CCF0 Bit 8 Bit 0 Bit8 BIT 0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8
Freescale Semiconductor, Inc...
$008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E
36 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0080 - $00AF
Address $009F $00A0 $00A1 $00A2 $00A3 $00A4 Name ATDDR7L ATDDR8H ATDDR8L ATDDR9H ATDDR9L ATDDR10H ATDDR10L ATDDR11H ATDDR11L ATDDR12H ATDDR12L ATDDR13H ATDDR13L ATDDR14H ATDDR14L ATDDR15H ATDDR15L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 Bit 5 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 Bit 4 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 Bit 3 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 Bit 2 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 Bit 1 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 Bit 0 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0
Freescale Semiconductor, Inc...
$00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00aE $00AF
$00B0 - $00BF
Address $00B0 $00BF Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$00C0 - $00C7
Address $00C0 $00E1 Name IBAD IBFD Read: Write: Read: Write:
IIC (Inter IC Bus)
Bit 7 ADR7 IBC7 Bit 6 ADR6 IBC6 Bit 5 ADR5 IBC5 Bit 4 ADR4 IBC4 Bit 3 ADR3 IBC3 Bit 2 ADR2 IBC2 Bit 1 ADR1 IBC1 Bit 0 0 IBC0
37 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$00C0 - $00C7
Address $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 Name IBCR IBSR IBDR Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
IIC (Inter IC Bus)
Bit 7 IBEN TCF D7 0 0 0 Bit 6 IBIE IAAS D6 0 0 0 Bit 5 MS/SL IBB D5 0 0 0 Bit 4 TX/RX IBAL D4 0 0 0 Bit 3 TXAK 0 D3 0 0 0 Bit 2 0 RSTA SRW D2 0 0 0 Bit 1 0 IBIF D1 0 0 0 Bit 0 IBSWAI RXAK D0 0 0 0
Freescale Semiconductor, Inc...
$00C8 - $00CF
Address $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL
SCI0 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
$00D0 - $00D7
Address $00D0 $00D1 $00D2 $00D3 $00D4 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1
SCI1 (Asynchronous Serial Interface) only on MC9S12H256
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Bit 5 0 SBR5 RSRC RIE RDRF Bit 4 SBR12 SBR4 M ILIE IDLE Bit 3 SBR11 SBR3 WAKE TE OR Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF
38 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$00D0 - $00D7
Address $00D5 $00D6 $00D7 Name SCI1SR2 SCI1DRH SCI1DRL Read: Write: Read: Write: Read: Write:
SCI1 (Asynchronous Serial Interface) only on MC9S12H256
Bit 7 0 R8 R7 T7 Bit 6 0 T8 R6 T6 Bit 5 0 0 R5 T5 Bit 4 0 0 R4 T4 Bit 3 0 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0
$00D8 - $00DF
Address $00D8 Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI0 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
Freescale Semiconductor, Inc...
$00D9 $00DA $00DB $00DC $00DD $00DE $00DF
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
$00E0 - $00FF
Address $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 $00E8 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC Test Only PWMSCLA Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PWM (Pulse Width Modulator 8 Bit 6 Channel)
Bit 7 0 0 0 0 0 0 0 0 Bit 7 Bit 6 0 0 0 PCKB2 0 CON45 0 0 6 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 5 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 4 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 2 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 1 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 Bit 0
39 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$00E0 - $00FF
Address $00E9 $00EA $00EB $00EC $00ED $00EE Name
Semiconductor, Inc.
PWM (Pulse Width Modulator 8 Bit 6 Channel)
Bit 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0 Bit 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 0 0 Bit 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 PWM5IN 0 Bit 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Freescale Semiconductor, Inc...
$00EF $00F0 $00F1 $00F2 $00F3 $00F4 $00F5 $00F6 $00F7 $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF
Bit 7 Read: PWMSCLB Bit 7 Write: 0 PWMSCNTA Read: Test Only Write: 0 PWMSCNTB Read: Test Only Write: Read: Bit 7 PWMCNT0 Write: 0 Read: Bit 7 PWMCNT1 Write: 0 Read: Bit 7 PWMCNT2 Write: 0 Read: Bit 7 PWMCNT3 Write: 0 Read: Bit 7 PWMCNT4 Write: 0 Read: Bit 7 PWMCNT5 Write: 0 Read: PWMPER0 Bit 7 Write: Read: PWMPER1 Bit 7 Write: Read: PWMPER2 Bit 7 Write: Read: PWMPER3 Bit 7 Write: Read: PWMPER4 Bit 7 Write: Read: PWMPER5 Bit 7 Write: Read: PWMDTY0 Bit 7 Write: Read: PWMDTY1 Bit 7 Write: Read: PWMDTY2 Bit 7 Write: Read: PWMDTY3 Bit 7 Write: Read: PWMDTY4 Bit 7 Write: Read: PWMDTY5 Bit 7 Write: Read: PWMSDN PWMIF Write: Read: 0 Reserved Write:
PWMRSTRT PWMLVL
PWM5INL PWM5ENA 0 0
0
0
40 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 Name FCLKDIV FSEC Reserved FCNFG FPROT FSTAT FCMD Reserved for Factory Test FADDRHI FADDRLO FDATAHI FDATALO Reserved
Flash Control Register (fts256k)
Bit 7 Bit 6 Read: FDIVLD PRDIV8 Write: Read: KEYEN NV6 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: FPOPEN NV6 Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 Bit 14 Write: Read: Bit 7 6 Write: Read: Bit 15 14 Write: Read: Bit 7 6 Write: Read: 0 0 Write: Bit 5 FDIV5 NV5 0 KEYACC FPHDIS PVIOL CMDB5 0 13 5 13 5 0 Bit 4 FDIV4 NV4 WRALL 0 FPHS1 ACCERR 0 0 12 4 12 4 0 Bit 3 FDIV3 NV3 0 0 FPHS0 0 0 0 11 3 11 3 0 Bit 2 FDIV2 NV2 0 0 FPLDIS BLANK CMDB2 0 10 2 10 2 0 Bit 1 FDIV1 SEC1 0 BKSEL1 FPLS1 0 0 0 9 1 9 1 0 Bit 0 FDIV0 SEC0 0 BKSEL0 FPLS0 0 CMDB0 0 Bit 8 Bit 0 Bit 8 Bit 0 0
Freescale Semiconductor, Inc...
$0106 $0107 $0108 $0109 $010A $010B $010C $010F
$0110 - $011B
Address $0110 $0111 $0112 $0113 $0114 $0115 $0116 $0117 $0118 Name ECLKDIV Reserved Reserved for Factory Test ECNFG EPROT ESTAT ECMD Reserved for Factory Test EADDRHI
EEPROM Control Register (eets4k)
Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: EPOPEN NV6 Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Bit 5 EDIV5 0 0 0 NV5 PVIOL CMDB5 0 0 Bit 4 EDIV4 0 0 0 NV4 ACCERR 0 0 0 Bit 3 EDIV3 0 0 0 EPDIS 0 0 0 0 Bit 2 EDIV2 0 0 0 EP2 BLANK CMDB2 0 10 Bit 1 EDIV1 0 0 0 EP1 0 0 0 9 Bit 0 EDIV0 0 0 0 EP0 0 CMDB0 0 Bit 8
41 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0110 - $011B
Address $0119 $011A $011B Name EADDRLO EDATAHI EDATALO Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
EEPROM Control Register (eets4k)
Bit 7 Bit 7 Bit 15 Bit 7 Bit 6 6 14 6 Bit 5 5 13 5 Bit 4 4 12 4 Bit 3 3 11 3 Bit 2 2 10 2 Bit 1 1 9 1 Bit 0 Bit 0 Bit 8 Bit 0
$011C - $011F
Address $011C $011F Name Reserved Read: Write:
Reserved for RAM Control Register
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Freescale Semiconductor, Inc...
$0120 - $0137
Address $0120 $0121 $0122 $0123 $0124 $0125 $0126 $0127 $0128 $0129 $012A $012B $012C $012D $012E $012F Name LCDCR0 LCDCR1 FPENR0 FPENR1 FPENR2 FPENR3 Reserved Reserved LCDRAM0 LCDRAM1 LCDRAM2 LCDRAM3 LCDRAM4 LCDRAM5 LCDRAM6 LCDRAM7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
Bit 7 LCDEN 0 FPEN7 FPEN15 FPEN23 FPEN31 0 0 FP1BP3 FP3BP3 FP5BP3 FP7BP3 FP9BP3 Bit 6 0 0 FPEN6 FPEN14 FPEN22 FPEN30 0 0 FP1BP2 FP3BP2 FP5BP2 FP7BP2 FP9BP2 Bit 5 LCLK2 0 FPEN5 FPEN13 FPEN21 FPEN29 0 0 FP1BP1 FP3BP1 FP5BP1 FP7BP1 FP9BP1 Bit 4 LCLK1 0 FPEN4 FPEN12 FPEN20 FPEN28 0 0 FP1BP0 FP3BP0 FP5BP0 FP7BP0 FP9BP0 Bit 3 LCLK0 0 FPEN3 FPEN11 FPEN19 FPEN27 0 0 FP0BP3 FP2BP3 FP4BP3 FP6BP3 FP8BP3 Bit 2 BIAS 0 FPEN2 FPEN10 FPEN18 FPEN26 0 0 FP0BP2 FP2BP2 FP4BP2 FP6BP2 FP8BP2 Bit 1 DUTY1
LCDSWAI
Bit 0 DUTY0
LCDRPSTP
FPEN1 FPEN9 FPEN17 FPEN25 0 0 FP0BP1 FP2BP1 FP4BP1 FP6BP1 FP8BP1
FPEN0 FPEN8 FPEN16 FPEN24 0 0 FP0BP0 FP2BP0 FP4BP0 FP6BP0 FP8BP0
FP11BP3 FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0 FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0 FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0
42 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0120 - $0137
Address $0130 $0131 $0132 $0133 $0134 $0135 Name LCDRAM8 LCDRAM9 LCDRAM10 LCDRAM11 LCDRAM12 LCDRAM13 LCDRAM14 LCDRAM15 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0 FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0 FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0 FP25BP3 FP25BP2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0 FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0 FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0 FP31BP3 FP31BP2 FP31BP1 FP31BP0 FP30BP3 FP30BP2 FP30BP1 FP30BP0
Freescale Semiconductor, Inc...
$0136 $0137
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D $014E Name
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Read: RXACT SYNCH CAN0CTL0 RXFRM CSWAI TIME Write: Read: 0 CAN0CTL1 CANE CLKSRC LOOPB LISTEN Write: Read: CAN0BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 Write: Read: CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 Write: Read: RSTAT1 RSTAT0 TSTAT1 CAN0RFLG WUPIF CSCIF Write: Read: CAN0RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 Write: Read: 0 0 0 0 0 CAN0TFLG Write: Read: 0 0 0 0 0 CAN0TIER Write: Read: 0 0 0 0 0 CAN0TARQ Write: Read: 0 0 0 0 0 CAN0TAAK Write: Read: 0 0 0 0 0 CAN0TBSEL Write: Read: 0 0 0 CAN0IDAC IDAM1 IDAM0 Write: Read: 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 CAN0RXERR Write:
TSEG12 TSEG11 TSEG10 TSTAT0 TSTATE0 TXE2 TXEIE2 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 0
RXERR2 RXERR1 RXERR0
43 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0140 - $017F
Address $014F $0150 $0153 $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F Name CAN0TXERR CAN0IDAR0 CAN0IDAR3 CAN0IDMR0 CAN0IDMR3 CAN0IDAR4 CAN0IDAR7 CAN0IDMR4 CAN0IDMR7 CAN0RXFG CAN0TXFG
Semiconductor, Inc.
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-3 Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-3 Write:
Freescale Semiconductor, Inc...
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $0160 Name Extended ID Standard ID CAN0RIDR0 Extended ID Standard ID CAN0RIDR1 Extended ID Standard ID CAN0RIDR2 Extended ID Standard ID CAN0RIDR3 CAN0RDSR0 CAN0RDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CAN0RDLR Write: Read: Reserved Write: Read: CAN0RTSRH Write: Read: CAN0RTSRL Write: Extended ID Read: CAN0TIDR0 Write: Standard ID Read: Write: Extended ID Read: CAN0TIDR1 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$0161
ID9
ID8
ID7
$0162
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$0163 $0164$016B $016C $016D $016E $016F
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7 ID28 ID10 ID20 ID2
TSR14 TSR6 ID27 ID9 ID19 ID1
TSR13 TSR5 ID26 ID8 ID18 ID0
TSR12 TSR4 ID25 ID7 SRR=1 RTR
TSR11 TSR3 ID24 ID6 IDE=1 IDE=0
TSR10 TSR2 ID23 ID5 ID17
TSR9 TSR1 ID22 ID4 ID16
TSR8 TSR0 ID21 ID3 ID15
$0170
$0171
44 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $0172 Name Extended ID CAN0TIDR2 Standard ID Extended ID CAN0TIDR3 Standard ID CAN0TDSR0 CAN0TDSR7 CAN0TDLR CON0TTBPR CAN0TTSRH CAN0TTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID14 Bit 6 ID13 Bit 5 ID12 Bit 4 ID11 Bit 3 ID10 Bit 2 ID9 Bit 1 ID8 Bit 0 ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$0173 $0174$017B $017C
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
Freescale Semiconductor, Inc...
$017D $017E $017F
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 - $01BF
Address $0180 $0181 $0182 $0183 $0184 $0185 $0186 $0187 $0188 $0189 $018A $018B $018C $018D Name
CAN1 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH CAN1CTL0 RXFRM CSWAI TIME WUPE SLPRQ INITRQ Write: Read: 0 SLPAK INITAK CAN1CTL1 CANE CLKSRC LOOPB LISTEN WUPM Write: Read: CAN1BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write: Read: CAN1BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 CAN1RFLG WUPIF CSCIF OVRIF RXF Write: Read: CAN1RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: Read: 0 0 0 0 0 CAN1TFLG TXE2 TXE1 TXE0 Write: Read: 0 0 0 0 0 CAN1TIER TXEIE2 TXEIE1 TXEIE0 Write: Read: 0 0 0 0 0 CAN1TARQ ABTRQ2 ABTRQ1 ABTRQ0 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 CAN1TAAK Write: Read: 0 0 0 0 0 CAN1TBSEL TX2 TX1 TX0 Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 CAN1IDAC IDAM1 IDAM0 Write: Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 0 0 0 Reserved Write:
45 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0180 - $01BF
Address $018E $018F $0190 $0193 $0194 $0197 $0198 $019B $019C $019F $01A0 $01AF $01B0 $01BF Name CAN1RXERR CAN1TXERR CAN1IDAR0 CAN1IDAR3 CAN1IDMR0 CAN1IDMR3 CAN1IDAR4 CAN1IDAR7 CAN1IDMR4 CAN1IDMR7 CAN1RXFG CAN1TXFG
Semiconductor, Inc.
CAN1 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-3 Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-3 Write:
Freescale Semiconductor, Inc...
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $01A0 Name Extended ID Standard ID CAN1RIDR0 Extended ID Standard ID CAN1RIDR1 Extended ID Standard ID CAN1RIDR2 Extended ID Standard ID CAN1RIDR3 CAN1RDSR0 CAN1RDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CAN1RDLR Write: Read: Reserved Write: Read: CAN1RTSRH Write: Read: CAN1RTSRL Write: Extended ID Read: CAN1TIDR0 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$01A1
ID9
ID8
ID7
$01A2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$01A3 $01A4$01AB $01AC $01AD $01AE $01AF
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7 ID28 ID10
TSR14 TSR6 ID27 ID9
TSR13 TSR5 ID26 ID8
TSR12 TSR4 ID25 ID7
TSR11 TSR3 ID24 ID6
TSR10 TSR2 ID23 ID5
TSR9 TSR1 ID22 ID4
TSR8 TSR0 ID21 ID3
$01B0
46 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $01B1 Name Extended ID CAN1TIDR1 Standard ID Extended ID CAN1TIDR2 Standard ID Extended ID CAN1TIDR3 Standard ID CAN1TDSR0 CAN1TDSR7 CAN1TDLR CON1TTBPR CAN1TTSRH CAN1TTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID20 ID2 ID14 Bit 6 ID19 ID1 ID13 Bit 5 ID18 ID0 ID12 Bit 4 SRR=1 RTR ID11 Bit 3 IDE=1 IDE=0 ID10 ID9 ID8 ID7 Bit 2 ID17 Bit 1 ID16 Bit 0 ID15
$01B2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$01B3 $01B4$01BB $01BC $01BD $01BE $01BF
Freescale Semiconductor, Inc...
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$01C0 - $01FF
Address $01C0 $01C1 $01C2 $01C3 $01C4 $01C5 $01C6 $01C7 $01C8 $01C9 $01CA $01CB Name MCCTL0 MCCTL1 MCPER (hi) MCPER (lo) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
MC (Motor Controller 10bit 12 channels)
Bit 7 Bit 6 Bit 5 Bit 4 Read: 0 MCPRE1 MCPRE0 MCSWAI Write: Read: 0 0 0 RECIRC Write: Read: 0 0 0 0 Write: Read: P7 P6 P5 P4 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Read: 0 0 0 0 Write: Bit 3 FAST 0 0 P3 0 0 0 0 0 0 0 0 Bit 2 DITH 0 P10 P2 0 0 0 0 0 0 0 0 Bit 1 0 0 P9 P1 0 0 0 0 0 0 0 0 Bit 0 MCTOIF MCTOIE P8 P0 0 0 0 0 0 0 0 0
47 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$01C0 - $01FF
Address $01CC $01CD $01CE $01CF $01D0 $01D1 Name Reserved Reserved Reserved Reserved MCCC0 MCCC1 MCCC2 MCCC3 MCCC4 MCCC5 MCCC6 MCCC7 MCCC8 MCCC9 MCCC10 MCCC11 Reserved Reserved Reserved Reserved MCDC0 (hi) MCDC0 (lo) MCDC1 (hi) MCDC1 (lo) MCDC2 (hi) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
MC (Motor Controller 10bit 12 channels)
Bit 7 0 0 0 0 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 0 0 0 0 S D7 S D7 S Bit 6 0 0 0 0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 0 0 0 0 S D6 S D6 S Bit 5 0 0 0 0 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 0 0 0 0 S D5 S D5 S Bit 4 0 0 0 0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 0 0 0 0 S D4 S D4 S Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S D3 S D3 S Bit 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D10 D2 D10 D2 D10 Bit 1 0 0 0 0 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 0 0 0 0 D9 D1 D9 D1 D9 Bit 0 0 0 0 0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 0 0 0 0 D8 D0 D8 D0 D8
Freescale Semiconductor, Inc...
$01D2 $01D3 $01D4 $01D5 $01D6 $01D7 $01D8 $01D9 $01DA $01DB $01DC $01DD $01DE $01DF $01E0 $01E1 $01E2 $01E3 $01E4
48 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$01C0 - $01FF
Address $01E5 $01E6 $01E7 $01E8 $01E9 $01EA Name MCDC2 (lo) MCDC3 (hi) MCDC3 (lo) MCDC4 (hi) MCDC4 (lo) MCDC5 (hi) MCDC5 (lo) MCDC6 (hi) MCDC6 (lo) MCDC7 (hi) MCDC7 (lo) MCDC8 (hi) MCDC8 (lo) MCDC9 (hi) MCDC9 (lo) MCDC10 (hi) MCDC10 (lo) MCDC11 (hi) MCDC11 (lo) Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
MC (Motor Controller 10bit 12 channels)
Bit 7 D7 S D7 S D7 S D7 S D7 S D7 S D7 S D7 S D7 S D7 0 0 0 0 0 Bit 6 D6 S D6 S D6 S D6 S D6 S D6 S D6 S D6 S D6 S D6 0 0 0 0 0 Bit 5 D5 S D5 S D5 S D5 S D5 S D5 S D5 S D5 S D5 S D5 0 0 0 0 0 Bit 4 D4 S D4 S D4 S D4 S D4 S D4 S D4 S D4 S D4 S D4 0 0 0 0 0 Bit 3 D3 S D3 S D3 S D3 S D3 S D3 S D3 S D3 S D3 S D3 0 0 0 0 0 Bit 2 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 0 0 0 0 0 Bit 1 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 0 0 0 0 0 Bit 0 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 0 0 0 0 0
Freescale Semiconductor, Inc...
$01EB $01EC $01ED $01EE $01EF $01F0 $01F1 $01F2 $01F3 $01F4 $01F5 $01F6 $01F7 $01F8 $01F9 $01FA $01FB $01FC
49 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$01C0 - $01FF
Address $01FD $01FE $01FF Name Reserved Reserved Reserved Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
MC (Motor Controller 10bit 12 channels)
Bit 7 0 0 0 Bit 6 0 0 0 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0
$0200 - $027F
Address $0200 Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 PTT7 PTIT7 DDRT7 RDRT7 PERT7 PPST7 0 0 PTS7 PTIS7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 0 0 0 Bit 6 PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 0 0 PTS6 PTIS6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 0 0 0 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 0 0 PTS5 PTIS5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 PTM5 PTIM5 DDRM5 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 0 0 PTS4 PTIS4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 PTM4 PTIM4 DDRM4 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 0 0 PTS3 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 0 0 PTS2 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 0 0 PTS1 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0 0 PTS0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0
Freescale Semiconductor, Inc...
$0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C $020D $020E $020F $0210 $0211 $0212
50 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0200 - $027F
Address $0213 $0214 $0215 $0216 $0217 $0218 Name RDRM PERM PPSM WOMM Reserved PTP PTIP DDRP RDRP PERP PPSP Reserved Reserved PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 PTH7 PTIH7 DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 0 0 0 0 0 PTH6 PTIH6 DDRH7 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 0 0 0 0 Bit 5 RDRM5 PERM5 PPSM5 Bit 4 RDRM4 PERM4 PPSM4 Bit 3 RDRM3 PERM3 PPSM3 Bit 2 RDRM2 PERM2 PPSM2 Bit 1 RDRM1 PERM1 PPSM1 Bit 0 RDRM0 PERM0 PPSM0
WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 0 0 PTH5 PTIH5 DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 0 0 0 0 0 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 0 0 PTH4 PTIH4 DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 0 0 0 0 0 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 0 0 PTH3 PTIH3 DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 PTJ3 PTIJ3 DDRJ3 RDRJ3 0 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 0 0 PTH2 PTIH2 DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 PTJ2 PTIJ2 DDRJ2 RDRJ2 0 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 0 0 PTH1 PTIH1 DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRJ1 RDRJ1 0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 0 0 PTH0 PTIH0 DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ0 RDRJ0
Freescale Semiconductor, Inc...
$0219 $021A $021B $021C $021D $021E $021F $0220 $0221 $0222 $0223 $0224 $0225 $0226 $0227 $0228 $0229 $022A $022B
51 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
$0200 - $027F
Address $022C $022D $022E $022F $0230 $0231 Name PERJ PPSJ PIEJ PIFJ PTL PTIL DDRL RDRL PERL PPSL Reserved Reserved PTU PTIU DDRU SRRU PERU PPSU Reserved Reserved PTV PTIV DDRV SRRV PERV Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
PIM (Port Integration Module)
Bit 7 0 0 0 0 PTL7 PTIL7 DDRL7 RDRL7 PERL7 PPSL7 0 0 PTU7 PTIU7 DDRU7 SRRU7 PERU7 PPSU7 0 0 PTV7 PTIV7 DDRV7 SRRV7 PERV7 Bit 6 0 0 0 0 PTL6 PTIL6 DDRL7 RDRL6 PERL6 PPSL6 0 0 PTU6 PTIU6 DDRU7 SRRU6 PERU6 PPSU6 0 0 PTV6 PTIV6 DDRV7 SRRV6 PERV6 Bit 5 0 0 0 0 PTL5 PTIL5 DDRL5 RDRL5 PERL5 PPSL5 0 0 PTU5 PTIU5 DDRU5 SRRU5 PERU5 PPSU5 0 0 PTV5 PTIV5 DDRV5 SRRV5 PERV5 Bit 4 0 0 0 0 PTL4 PTIL4 DDRL4 RDRL4 PERL4 PPSL4 0 0 PTU4 PTIU4 DDRU4 SRRU4 PERU4 PPSU4 0 0 PTV4 PTIV4 DDRV4 SRRV4 PERV4 Bit 3 PERJ3 PPSJ3 PIEJ3 PIFJ3 PTL3 PTIL3 DDRL3 RDRL3 PERL3 PPSL3 0 0 PTU3 PTIU3 DDRU3 SRRU3 PERU3 PPSU3 0 0 PTV3 PTIV3 DDRV3 SRRV3 PERV3 Bit 2 PERJ2 PPSJ2 PIEJ2 PIFJ2 PTL2 PTIL2 DDRL2 RDRL2 PERL2 PPSL2 0 0 PTU2 PTIU2 DDRU2 SRRU2 PERU2 PPSU2 0 0 PTV2 PTIV2 DDRV2 SRRV2 PERV2 Bit 1 PERJ1 PPSJ1 PIEJ1 PIFJ1 PTL1 PTIL1 DDRL1 RDRL1 PERL1 PPSL1 0 0 PTU1 PTIU1 DDRU1 SRRU1 PERU1 PPSU1 0 0 PTV1 PTIV1 DDRV1 SRRV1 PERV1 Bit 0 PERJ0 PPSJ0 PIEJ0 PIFJ0 PTL0 PTIL0 DDRL0 RDRL0 PERL0 PPSL0 0 0 PTU0 PTIU0 DDRU0 SRRU0 PERU0 PPSU0 0 0 PTV0 PTIV0 DDRV0 SRRV0 PERV0
Freescale Semiconductor, Inc...
$0232 $0233 $0234 $0235 $0236 $0237 $0238 $0239 $023A $023B $023C $023D $023E $023F $0240 $0241 $0242 $0243 $0244
52 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
$0200 - $027F
Address $0245 $0246 $0247 $0248 $0249 $024A Name PPSV Reserved Reserved PTW PTIW DDRW SRRW PERW PPSW Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 PPSV7 0 0 PTW7 PTIW7 DDRW7 SRRW7 PERW7 PPSW7 0 0 0 Bit 6 PPSV6 0 0 PTW6 PTIW6 DDRW7 SRRW6 PERW6 PPSW6 0 0 0 Bit 5 PPSV5 0 0 PTW5 PTIW5 DDRW5 SRRW5 PERW5 PPSW5 0 0 0 Bit 4 PPSV4 0 0 PTW4 PTIW4 DDRW4 SRRW4 PERW4 PPSW4 0 0 0 Bit 3 PPSV3 0 0 PTW3 PTIW3 DDRW3 SRRW3 PERW3 PPSW3 0 0 0 Bit 2 PPSV2 0 0 PTW2 PTIW2 DDRW2 SRRW2 PERW2 PPSW2 0 0 0 Bit 1 PPSV1 0 0 PTW1 PTIW1 DDRW1 SRRW1 PERW1 PPSW1 0 0 0 Bit 0 PPSV0 0 0 PTW0 PTIW0 DDRW0 SRRW0 PERW0 PPSW0 0 0 0
Freescale Semiconductor, Inc...
$024B $024C $024D $024E $024F $0250 $027F
$0280 - $03FF
Address $0280 $03FF Name Reserved Read: Write:
Reserved
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL at addresses $001A,$001B, respectively. The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID numbers. Table 1-5 Assigned Part ID Numbers
Device MC9S12H256 MC9S12H256 Mask Set Number 0K78X 1K78X Part ID1 $1000 $1001
53 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-6 shows the read-only values of these registers. Refer to section Module Mapping and Control (MMC) of HCS12 Core User Guide for further details.
Table 1-6 Memory size registers
Register name MEMSIZ0 MEMSIZ1 Value $25 $81
Freescale Semiconductor, Inc...
54
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12H256 is available in a 112-pin and 144-pin quad flat pack (LQFP), the MC9S12H128 is available in a 112-pin quad flat pack (LQFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
Freescale Semiconductor, Inc...
NOTE:
In expanded narrow modes the lower byte data is multiplexed with higher byte data through pins 64-71 on the 112-pin LQFP or through pins 111-118 on the 144-pin LQFP version.
55 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/ECS/ROMONE/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
Freescale Semiconductor, Inc...
M0C0M/PU0 M0C0P/PU1 M0C1M/PU2 M0C1P/PU3 VDDM1 VSSM1 M1C0M/PU4 M1C0P/PU5 M1C1M/PU6 M1C1P/PU7 M2C0M/PV0 M2C0P/PV1 M2C1M/PV2 M2C1P/PV3 VDDM2 VSSM2 M3C0M/PV4 M3C0P/PV5 M3C1M/PV6 M3C1P/PV7 M4C0M/PW0 M4C0P/PW1 M4C1M/PW2 M4C1P/PW3 VDDM3 VSSM3 M5C0M/PW4 M5C0P/PW5
M5C1M/PW6 M5C1P/PW7 PWM0/PP0 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2
Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128
56 For More Information On This Product, Go to: www.freescale.com
MODC/TAGHI/BKGD
RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3 RXCAN1/PM4 TXCAN1/PM5 MODA/IPIP0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MC9S12H-Family 112 LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 PJ3/KWJ3 PJ2/KWJ2 PJ1/KWJ1 PJ0/KWJ0 VSSX1 VDDX1 PK7/ECS/ROMONE/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL7/FP31 PL6/FP30 PL5/FP29 PL4/FP28 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6 M0C0M/PU0 M0C0P/PU1 M0C1M/PU2 M0C1P/PU3 VDDM1 VSSM1 M1C0M/PU4 M1C0P/PU5 M1C1M/PU6 M1C1P/PU7 KWH0/PH0 KWH1/PH1 KWH2/PH2 KWH3/PH3 M2C0M/PV0 M2C0P/PV1 M2C1M/PV2 M2C1P/PV3 VDDM2 VSSM2 M3C0M/PV4 M3C0P/PV5 M3C1M/PV6 M3C1P/PV7 KWH4/PH4 KWH5/PH5 KWH6/PH6 KWH7/PH7 M4C0M/PW0 M4C0P/PW1 M4C1M/PW2 M4C1P/PW3 VDDM3 VSSM3 M5C0M/PW4 M5C0P/PW5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
Freescale Semiconductor, Inc...
MC9S12H-Family 144 LQFP
Pins shown in BOLD are not available in the 112 LQFP package
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
M5C1M/PW6 M5C1P/PW7 PWM0/PP0 PWM1/PP1 PWM2/PP2 PWM3/PP3 PWM4/PP4 PWM5/PP5 RXD0/PS0 TXD0/PS1 RXD1/PS2 TXD1/PS3 VSS2 VDDR VDDX2 VSSX2 MODC/TAGHI/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SDA/PM0 SCL/PM1 RXCAN0/PM2 TXCAN0/PM3 RXCAN1PM4 TXCAN1/PM5 MODA/IPIPE0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 2-2 Pin Assignments in 144-pin LQFP for MC9S12H256
57 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
2.2 Signal Properties Summary
Table 2-1 summarizes all pin functions.
NOTE:
Bold entries determine pins not available on 112-pin LQFP. Table 2-1 Signal Properties
Pin Name Pin Name Function 1 Function 2
EXTAL XTAL RESET TEST XFC BKGD PAD[7:0] PAD[15:8] PA[7:0] PB[7:0] PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PH[7:0] PJ[3:0] PK7 PK[3:0] PL[3:0] PL[7:4] -- -- -- -- -- TAGHI AN[7:0] AN[15:8] FP[15:8] FP[7:0] FP22 IPIPE1 IPIPE0 ECLK FP21 FP20 IRQ XIRQ KWH[7:0] KWJ[3:0] FP23 BP[3:0] FP[19:16] FP[31:28]
Pin Name Function 3
-- -- -- -- -- MODC -- -- ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] XCLKS MODB MODA -- LSTRB R/W -- -- -- -- ECS XADDR[17:14] -- --
Pin Name Powered Function 4 by
-- -- -- -- -- -- -- -- -- -- NOACC -- -- -- TAGLO -- -- -- -- -- ROMONE -- -- -- VDDPLL VDDPLL VDDX2 VDDX2 VDDPLL VDDX2 VDDA VDDA VDDX1 VDDX1 VDDX1 VDDX2 VDDX2 VDDX2 VDDX1 VDDX1 VDDX2 VDDX2 VDDM VDDX1 VDDX1 VDDX1 VDDX1 VDDX1
Internal Pull Resistor Reset CTRL State
Description
Oscillator Pins None None External Reset Pin Test Input PLL Loop Filter Always Up None PUCR/ PUPAE PUCR/ PUPBE PUCR/ PUPEE Up Background Debug, Tag High, Mode Pin Port AD Inputs, Analog Inputs (ATD) None Port AD Inputs, Analog Inputs (ATD) Port A I/O, Multiplexed Address/Data Port B I/O, Multiplexed Address/Data Port E I/O, Access, Clock Select, LCD driver Port E I/O, Pipe Status, Mode Input Port E I/O, Pipe Status, Mode Input Port E I/O, Bus Clock Output PUCR/ PUPEE Mode de- Port E I/O, LCD driver, Byte Strobe, pendent Tag Low Port E I/O, R/W in expanded modes Up PERH/ PPSH PERJ/ PPSJ PUCR/ PUPKE PERL/ PPSL Port E Input, Maskable Interrupt Port E Input, Non Maskable Interrupt
Freescale Semiconductor, Inc...
Down Down Down
While RESET pin is low: Down
Disabled Port H I/O, Interrupts Disabled Port J I/O, Interrupts Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, LCD driver, Extended Addresses Port L I/O, LCD drivers Port L I/O, LCD drivers
Down
Down
58 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Pin Name Pin Name Function 1 Function 2
PM5 PM4 PM3 PM2 PM1 PM0 PP[5:2] PP[1:0] PS7 PS6 TXCAN1 RXCAN1 TXCAN0 RXCAN0 SCL SDA PWM[5:2] PWM[1:0] SS SCK MOSI MISO TXD1 RXD1 TXD0 RXD0 IOC[7:4] IOC[3:0] M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P, M5C1M M5C1P
Pin Name Function 3
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FP[27:24]
Pin Name Powered Function 4 by
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX1 VDDX1
Internal Pull Resistor Reset CTRL State
Description
Port M I/O, TX of CAN1 Port M I/O, RX of CAN1
PERM/ PPSM
Disabled
Port M I/O, TX of CAN0 Port M I/O, RX of CAN0 Port M I/O, SCL of IIC Port M I/O, SDA of IIC
PERP/ PPSP
Disabled
Port P I/O, PWM channels Port P I/O, PWM channels Port S I/O, SS of SPI Port S I/O, SCK of SPI Port S I/O, MOSI of SPI
Freescale Semiconductor, Inc...
PS5 PS4 PS3 PS2 PS1 PS0 PT[7:4] PT[3:0]
PERS/ PPSS
Disabled
Port S I/O, MISO of SPI Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0 Port T I/O, Timer channels
PERT/ PPST
Down
Port T I/O, Timer channels, LCD driver Port U I/O, Motor0 of MC
PU[3:0]
--
--
VDDM PERU/ PPSU Disabled
PU[7:4]
--
--
VDDM
Port U I/O, Motor1 of MC
PV[3:0]
--
--
VDDM PERV/ PPSV Disabled
Port V I/O, Motor2 of MC
PV[7:4]
--
--
VDDM
Port V I/O, Motor3 of MC
PW[3:0]
--
--
VDDM PERW/ PPSW Disabled
Port W I/O, Motor4 of MC
PW[7:4]
--
--
VDDM
Port W I/O, Motor5 of MC
59 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET -- External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
2.3.3 TEST -- Test Pin
Freescale Semiconductor, Inc...
This pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 XFC -- PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter.
2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET.
2.3.6 PAD[15:8] / AN[15:8] -- Port AD Input Pins [15:8]
PAD15-PAD8 are general purpose input pins and analog inputs for the analog to digital converter.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.7 PAD[7:0] / AN[7:0] -- Port AD Input Pins [7:0]
PAD7-PAD0 are general purpose input pins and analog inputs for the analog to digital converter.
2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general purpose input or output pins. They can be configured as frontplane segment driver outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
60 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general purpose input or output pins. They can be configured as frontplane segment driver outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.10 PE7 / FP22 / XCLKS / NOACC -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP22 of the LCD module. The XCLKS signal selects between an external clock or oscillator configuration during reset. The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is latched at the rising edge of RESET. If the input is a logic high the EXTAL pin is configured for an external clock drive. If input is a logic low an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus.
Freescale Semiconductor, Inc...
2.3.11 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low.
2.3.12 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low.
2.3.13 PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
2.3.14 PE3 / FP21 / LSTRB / TAGLO -- Port E I/O Pin 3
PE3 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP21 of the LCD module. In MCU expanded modes of operation, LSTRB is used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
61 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
2.3.15 PE2 / FP20 / R/W -- Port E I/O Pin 2
PE2 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP20 of the LCD module. In MCU expanded modes of operations, this pin performs the read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.16 PE1 / IRQ -- Port E Input Pin 1
PE1 is a general purpose input pin and also the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.17 PE0 / XIRQ -- Port E Input Pin 0
Freescale Semiconductor, Inc...
PE0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PH[7:0] / KWH[7:0] -- Port H I/O Pins [7:0]
PH7-PH0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.19 PJ[3:0] / KWJ[3:0] -- Port J I/O Pins [3:0]
PJ3-PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.and are shared with the interrupt function.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.20 PK7 / FP23 / ECS / ROMONE -- Port K I/O Pin 7
PK7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP23 of the LCD module. During MCU expanded modes of operation, this pin is used as the emulation chip select signal (ECS). During reset of the MCU to normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the state of this pin is latched to the ROMON bit.
2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] -- Port K I/O Pins [3:0]
PK3-PK0 are general purpose input or output pins. They can be configured as backplane segment driver outputs BP3-BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the expanded address XADDR[17:14] for the external bus.
62 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 2.3.22 PL[7:4] / FP[31:28] -- Port L I/O Pins [7:4]
PL7-PL4 are general purpose input or output pins. They can be configured as frontplane segment driver outputs FP31-FP28 of the LCD module.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.23 PL[3:0] / FP[19:16] -- Port L I/O Pins [3:0]
PL3-PL0 are general purpose input or output pins. They can be configured as frontplane segment driver outputs FP19-FP16 of the LCD module.
2.3.24 PM5 / TXCAN1 -- Port M I/O Pin 5
Freescale Semiconductor, Inc...
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the Motorola Scalable Controller Area Network controller 1 (CAN1)
2.3.25 PM4 / RXCAN1 -- Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN1 of the Motorola Scalable Controller Area Network controller 1 (CAN1)
2.3.26 PM3 / TXCAN0 -- Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the Motorola Scalable Controller Area Network controller 0 (CAN0)
2.3.27 PM2 / RXCAN0 -- Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN0 of the Motorola Scalable Controller Area Network controller 0 (CAN0)
2.3.28 PM1 / SCL -- Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the serial clock pin SCL of the Inter-IC Bus Interface (IIC).
NOTE:
This pin is not available in the 112-pin LQFP version.
2.3.29 PM0 / SDA -- Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the serial data pin SDA of the Inter-IC Bus Interface (IIC).
NOTE:
This pin is not available in the 112-pin LQFP version.
63 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
2.3.30 PP[5:2] / PWM[5:2] -- Port P I/O Pins [5:2]
PP5-PP2 are general purpose input or output pins. They can be configured as Pulse Width Modulator (PWM) channel outputs PWM5-PWM2.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.31 PP[1:0] / PWM[1:0] -- Port P I/O Pins [1:0]
PP1-PP0 are general purpose input or output pins. They can be configured as Pulse Width Modulator (PWM) channel outputs PWM1-PWM0.
2.3.32 PS7 / SS -- Port S I/O Pin 7
Freescale Semiconductor, Inc...
PS7 is a general purpose input or output pin. It can be configured as slave select pin SS of the Serial Peripheral Interface (SPI).
2.3.33 PS6 / SCK -- Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as serial clock pin SCK of the Serial Peripheral Interface (SPI).
2.3.34 PS5 / MOSI -- Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as the master output (during master mode) or slave input (during slave mode) pin MOSI of the Serial Peripheral Interface (SPI).
2.3.35 PS4 / MISO -- Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO for the Serial Peripheral Interface (SPI).
2.3.36 PS3 / TXD1 -- Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as transmit pin TXD1 of the Serial Communication Interface 1 (SCI1).
NOTE:
This pin is not available in the 112-pin LQFP version.
2.3.37 PS2 / RXD1 -- Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as receive pin RXD1 of the Serial Communication Interface 1 (SCI1).
NOTE:
This pin is not available in the 112-pin LQFP version.
64 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 2.3.38 PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as transmit pin TXD0 of the Serial Communication Interface 0 (SCI0).
2.3.39 PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as receive pin RXD0 of the Serial Communication Interface 0 (SCI0).
2.3.40 PT[7:4] / IOC[7:4] -- Port T I/O Pins [7:4]
Freescale Semiconductor, Inc...
PT7-PT4 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC4 of the Timer (TIM).
2.3.41 PT[3:0] / IOC[3:0] / FP[27:24] -- Port T I/O Pins [3:0]
PT3-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC3-IOC0 of the Timer (TIM). They can be configured as frontplane segment driver outputs FP27-FP24 of the LCD module.
2.3.42 PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M -- Port U I/O Pins [7:4]
PU7-PU4 are general purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high state.
2.3.43 PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M -- Port U I/O Pins [3:0]
PU3-PU0 are general purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state.
2.3.44 PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M -- Port V I/O Pins [7:4]
PV7-PV4 are general purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state.
65 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M -- Port V I/O Pins [3:0]
PV3-PV0 are general purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state.
2.3.46 PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M -- Port W I/O Pins [7:4]
PW7-PW4 are general purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high state.
Freescale Semiconductor, Inc...
2.3.47 PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M -- Port W I/O Pins [3:0]
PW3-PW0 are general purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high state.
2.4 Power Supply Pins
MC9S12H256 power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application (21.2 Recommended PCB layout). Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded (Table 21-1).
2.4.1 VDDR -- External Power Pin
VDDR is the power supply pin for the internal voltage regulator.
2.4.2 VDDX1, VDDX2, VSSX1, VSSX2 -- External Power and Ground Pins
VDDX1, VDDX2, VSSX1 and VSSX2 are the power supply and ground pins for input/output drivers.VDDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.
66 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 2.4.3 VDD1, VSS1, VSS2 -- Core Power Pins
VDD1, VSS1 and VSS2 are the core power and ground pins and related to the voltage regulator output. These pins serve as connection points for filter capacitors. VSS1 and VSS2 are internally connected.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog to digital converter.
2.4.5 VDDM1, VDDM2, VDDM3 -- Power Supply Pins for Motor 0 to 5
Freescale Semiconductor, Inc...
VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U,V and W. VDDM1, VDDM2 and VDDM3 are internally connected.
2.4.6 VSSM1, VSSM2, VSSM3 -- Ground Pins for Motor 0 to 5
VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U,V and W. VSSM1, VSSM2 and VSSM3 are internally connected.
2.4.7 VLCD -- Power Supply Reference Pin for LCD driver
VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast.
2.4.8 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the voltage reference pins for the analog to digital converter.
2.4.9 VDDPLL, VSSPLL -- Power Supply Pins for PLL
VDDPLL and VSSPLL are the PLL supply pins and serve as connection points for external loop filter components.
NOTE:
No load allowed except for bypass capacitors.
67 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
68 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation.
S12_CORE
Freescale Semiconductor, Inc...
core clock
Flash RAM EEPROM EXTAL TIM ATD CRG bus clock oscillator clock XTAL PWM SCI0, SCI1 SPI CAN0, CAN1 IIC MC LCD PIM
Figure 3-1 Clock Connections
69 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
70 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12H256. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device.
4.2 Modes of Operation
Freescale Semiconductor, Inc...
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. Table 4-1 Mode Selection
MODC
0 0 0 0 1 1 1 1
MODB
0 0 1 1 0 0 1 1
MODA
0 1 0 1 0 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide) (Motorola Use Only), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral (Motorola Use Only); BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
71 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. 4.2.1.1 Normal Single-Chip Mode There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their internal pull-ups disabled. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated Port E pins. In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.1.2 Normal Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose I/O pins. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
Freescale Semiconductor, Inc...
72 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing "1" to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications. The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 4.2.1.3 Normal Expanded Narrow Mode
Freescale Semiconductor, Inc...
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to "1" in this mode, the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. 4.2.1.4 Internal Visibility Internal visibility is available when the MCU is operating in expanded wide modes or special narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register.
73 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. 4.2.1.5 Emulation Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in special mode are restricted. 4.2.1.6 Emulation Expanded Narrow Mode Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1. Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data D0 is associated with PB0. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in special mode are restricted.
Freescale Semiconductor, Inc...
4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development.
74 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
4.2.2.1 Special Single-Chip Mode When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.
Freescale Semiconductor, Inc...
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.2.2 Special Test Mode (Motorola Use Only) In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.2.3 Test Operating Mode (Motorola Use Only)
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip peripherals. 4.2.3.1 Peripheral Mode This mode is intended for Motorola factory testing of the MCU. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions.
75 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * * * * Protection of the contents of FLASH, Protection of the contents of EEPROM, Operation in single-chip mode, Operation from external memory with internal FLASH and EEPROM disabled.
Freescale Semiconductor, Inc...
The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
76 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode.
Freescale Semiconductor, Inc...
77 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
78 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Freescale Semiconductor, Inc...
Table 5-1 Reset and Interrupt Vector Table
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB Port J Port H
Interrupt Source
External or Power On Reset Clock Monitor fail reset COP failure reset SWI XIRQ IRQ Real Time Interrupt Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 Timer channel 4 Timer channel 5 Timer channel 6 Timer channel 7 Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI SCI0 SCI1 ATD0
CCR Mask
None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None COPCTL (CME, FCME) COP rate select None None None INTCR (IRQEN) RTICTL (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOI) PACTL (PAOVI) PACTL (PAI) SP0CR1 (SPIE) SC0CR2 (TIE, TCIE, RIE, ILIE) SC1CR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) PTJIF (PTJIE) PTHIF (PTHIE)
HPRIO Value to Elevate
$F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $CE $CC
Unimplemented instruction trap None
Reserved
Reserved
79 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table 5-1 Reset and Interrupt Vector Table
Vector Address
$FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, $FFB7 EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CAN1 transmit CRG PLL lock CRG Self Clock Mode Reserved IIC Bus I-Bit Reserved Reserved I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit EECTL (CCIE, CBEIE) FCTL (CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE[2:0]) CAN0RIER (WUPIE) CAN1RIER (CSCIE, OVRIE) CAN1RIER (RXFIE) CAN1TIER (TXEIE[2:0]) $BA $B8 $B6 $B4 $B2 $B0 $AE $AC $AA $A8 IBCR (IBIE) $C0
Interrupt Source
CCR Mask
I-Bit I-Bit
Local Enable
CRGINT (LOCKIE) CRGINT (SCMIE)
HPRIO Value to Elevate
$C6 $C4
Reserved
Freescale Semiconductor, Inc...
$FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FFAE, $FFAF $FFAC, $FFAD $FFAA, $FFAB $FFA8, $FFA9 $FF98 to $FFA7 $FF96, $FF97 $FF9E to $FF95 $FF8C, $FF8D $FF80 to $FF8B
Reserved Motor Control Timer Overflow I-Bit MCCTL1 (MCOCIE) $96
Reserved PWM Emergency Shutdown I-Bit PWMSDN(PWMIE) $8C
Reserved
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
NOTE:
For devices assembled in 112-pin LQFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
80 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset.
Freescale Semiconductor, Inc...
81 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
82 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
Freescale Semiconductor, Inc...
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active high (see 2.3.10 PE7 / FP22 / XCLKS / NOACC -- Port E I/O Pin 7).
Section 8 Timer (TIM) Block Description
Consult the TIM_16B8C Block User Guide for information about the Timer module.
Section 9 Analog to Digital Converter (ATD) Block Description
Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 11 Serial Communications Interface (SCI) Block Description
83 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
There are two Serial Communications Interfaces (SCI0 and SCI1) implemented on the MC9S12H256 device and one SCI (SCI0) on MC9S12H128. Consult the SCI Block User Guide for information about each Serial Communications Interface module.
Section 12 Serial Peripheral Interface (SPI) Block Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.
Freescale Semiconductor, Inc...
Section 13 Pulse Width Modulator (PWM) Block Description
Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator module.
Section 14 Flash EEPROM 256K Block Description
Consult the FTS256K Block User Guide for information about the flash module.
Section 15 EEPROM 4K Block Description
Consult the EETS4K Block User Guide for information about the EEPROM module.
Section 16 RAM Block Description
The RAM module does not contain any control registers. Thus no Block User Guide is available. This module supports single-cycle misaligned word accesses without wait states.
Section 17 Liquid Crystal Display Driver (LCD) Block Description
Consult the LCD_32F4B Block User Guide for information about the Liquid Crystal Display Driver module.
Section 18 MSCAN Block Description
84 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult the MSCAN Block User Guide for information on each MSCAN.
Section 19 PWM Motor Control (MC) Block Description
Consult the MC_10B12C Block User Guide for information about the PWM Motor Control module.
Section 20 Port Integration Module (PIM) Block Description
Consult the PIM_9H256 Block User Guide for information about the Port Integration Module.
Freescale Semiconductor, Inc...
Section 21 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
21.1 Device-specific information
21.1.1 VREGEN
There is no VREGEN pin implemented on this device.
21.1.2 Modes of Operation
21.1.2.1 Run Mode VREG enters run mode whenever the CPU is neither in Stop nor in Pseudo Stop mode. Both regulating loops operate in Run mode with full performance. 21.1.2.2 Standby Mode VREG enters Standby mode when the CPU operates either in Stop or in Pseudo Stop mode. The supply of the core logic as well as the oscillators are derived from two voltage clamps. Standby mode minimizes quiescent current drawn by the voltage regulator block. 21.1.2.3 Shutdown Mode VREG Shutdown mode is not available on MC9S12H family devices.
85 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
21.2 Recommended PCB layout
Figure 21-1 LQFP112 recommended PCB layout
C8
VSSX1
VDDX1
VDDM1 C7
Freescale Semiconductor, Inc...
VSSM1 VSS1 C1 VDD1
VDDM2 C6 VSSM2
VDDA
VDDM3 C2 C5 VSSM3 VSSA
C3
C4
VDDR/
C14
C9
C10
C11
VDDX2
Q1 C12 R1 C13 VSSPLL VDDPLL
86 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Figure 21-2 LQFP144 recommended PCB layout
C8 VDDX1
VSSX1
VDDM1 C7
Freescale Semiconductor, Inc...
VSSM1 VSS1 C1 VDD1
VDDM2 C6 VSSM2
VDDA
VDDM3 C2 C5 VSSM3 VSSA
C3
C4
VDDR/
C9
VDDX2
C14
C10 Q1
C11
For More Information On This Product, Go to: www.freescale.com
C12 R1
C13 VSSPLL VDDPLL
87
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table 21-1 Recommended Components
Component
C1 C2 C3 C4 C5 C6 C7
Purpose
VDD1 filter cap VDDA filter cap VDDX2 filter cap VDDR filter cap VDDM3 filter cap VDDM2 filter cap VDDM1 filter cap VDDX1 filter cap VDDPLL filter cap OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap DC cutoff cap PLL loop filter res Quartz/Resonator
Type
ceramic X7R X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum ceramic X7R
Value
100 .. 220nF >=100nF >=100nF >=100nF >=100nF >=100nF >=100nF >=100nF 100nF .. 220nF
Freescale Semiconductor, Inc...
C8 C9 C10 C11 C12 C13 C14 R1 Q1
See CRG Block User Guide
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: * * * * * * * Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible to the corresponding pins(C1 - C9). Central point of the ground star should be the VSS1 pin. Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and VSSM1,2,3. VSSPLL must be directly connected to VSS1. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10, C11, C14 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins.
88 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Appendix A Electrical Characteristics
A.1 General
This supplement contains the most accurate electrical information for the MC9S12H256 and MC9S12H128 microcontroller available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
Freescale Semiconductor, Inc...
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.
NOTE:
P:
This classification is shown in the column labeled "C" in the parameter tables where appropriate.
Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12H256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. The VDDX1/VSSX1 and VDDX2/VSSX2 pairs supply the I/O pins except PH, PU, PV and PW. VDDR supplies the internal voltage regulator. VDDM1/VSSM1, VDDM2/VSSM2 and VDDM3/VSSM3 pairs supply the ports PH, PU, PV and PW.
89 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX1, VDDX2, VDDM as well as VSSA, VSSX1, VSSX2 and VSSM are connected by anti-parallel diodes for ESD protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDM, VDDR and VDDX1/2; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX1/2, VDDM and VDDR pins. VDD is used for VDD1 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDDPLL.
Freescale Semiconductor, Inc...
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
90 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Freescale Semiconductor, Inc...
Table A-1 Absolute Maximum Ratings1
Num
1 2 3 4 5 6 7 8 9 10
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 2 PLL Supply Voltage 2 Voltage difference VDDX1 to VDDX2 to VDDM and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins except PU, PV and PW 3 Instantaneous Maximum Current Single pin limit for Port PU, PV and PW 4 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL5 Instantaneous Maximum Current Single pin limit for TEST 6 Storage Temperature Range
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST ID
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25
Max
6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25
Unit
V V V V V V V V V mA
11 12 13 14
I
D
-55 -25 -0.25 - 65
+55 +25 0 155
mA mA mA C
IDL IDT T
stg
NOTES: 1. Beyond absolute maximum ratings device might be damaged. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX1/2 and VDDX1/2, VSSM and VDDM or VSSA and VDDA. 4. Ports PU, PV, PW are internally clamped to VSSM and VDDM.
91 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
5. Those pins are internally clamped to VSSPLL and VDDPLL. 6. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Freescale Semiconductor, Inc...
Model
Series Resistance
Description
Symbol
R1 C - R1 C -
Value
1500 100 - 3 3 0 200 - 3 3 -2.5 7.5
Unit
pF
Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit
pF
V V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
1 2 3 4
Rating
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
- - - -
Unit
V V V mA
C Human Body Model (HBM) C Machine Model (MM) C Charge Device Model (CDM) Latch-up Current at TA = 125C C positive negative Latch-up Current at TA = 27C C positive negative
5
ILAT
-
mA
92 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating Symbol
VDD5 VDD VDDPLL VDDX VSSX fosc fbus
Min
4.5 2.35 2.35 -0.1 -0.1 0.5 0.5
Typ
5 2.5 2.5 0 0 - -
Max
5.25 2.75 2.75 0.1 0.1 16 16
Unit
V V V V V MHz MHz
I/O, Regulator and Analog Supply Voltage
Freescale Semiconductor, Inc...
Digital Logic Supply Voltage 1 PLL Supply Voltage 2 Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12H256C, MC9S12H128C Operating Junction Temperature Range Operating Ambient Temperature Range 2 MC9S12H256V, MC9S12H128V Operating Junction Temperature Range Operating Ambient Temperature Range 2 MC9S12H256M, MC9S12H128M Operating Junction Temperature Range Operating Ambient Temperature Range 2
TJ T
A
-40 -40
- 27
100 85
C C
TJ TA
-40 -40
- 27
120 105
C C
T
J
-40 -40
- 27
140 125
C C
TA
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
93 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO
Freescale Semiconductor, Inc...
P INT = Chip Internal Power Dissipation, [W]
P INT = I DDR V DDR + I DDA V DDA
P IO =
RDSON IIOi
i
2
PIO is the sum of all output currents on I/O ports associated with VDDX1,2 and VDDM1,2,3. Table A-5 Thermal Package Characteristics1
Num C
1 2 3 4
Rating
Symbol
JA JA JA JA
Min
- - - -
Typ
- - - -
Max
54 41 45 37
Unit
oC/W oC/W oC/W oC/W
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3
T Thermal Resistance LQFP 144, single sided PCB T Thermal Resistance LQFP 144, double sided PCB with 2 internal planes
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
94 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Freescale Semiconductor, Inc...
95 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 P Input High Voltage P Input Low Voltage C Input Hysteresis
Rating
Symbol
V
IH IL
Min
0.65*VDD5 VSS5 - 0.3
Typ
- - 250
Max
VDD5 + 0.3 0.35*VDD5
Unit
V V mV A
V V
HYS
4
Input Leakage Current except PU, PV, PW (pins in P high impedance input mode)1 Vin = VDD5 or VSS5 Input Leakage Current PU, PV, PW (pins in high P impedance input mode)2 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode, except PU, PV and PW) P Partial Drive I OH = -1.0mA Full Drive IOH = -10mA Output Low Voltage (pins in output mode except PU, PV and PW) P Partial Drive I OL = +1.0mA Full Drive IOL = +10mA
Iin
-1.0
-
1.0
5
Iin
-2.5
-
2.5
A
Freescale Semiconductor, Inc...
6
VOH
VDD5 - 0.8
-
-
V
7
V
OL
-
-
0.8
V
8 9
Output High Voltage (pins PU, PV and PW in output P mode) I OH = -20mA Output Low Voltage (pins PU, PV and PW in output P mode) I OL = +20mA Output Rise Time (pins PU, PV and PW in output P mode with slew control enabled) VDD5=5V, Rload=1K, 10% to 90% of VOH Output Fall Time (pins PU, PV and PW in output P mode with slew control enabled) VDD5=5V, Rload=1K, 10% to 90% of VOH Internal Pull Up Device Current, P tested at V Max.
IL
V
OH
VDD5 - 0.32 VDD5 - 0.2 - .2
- 0.32
V V
V
OL
10
tr
60
100
130
ns
11
tf
60
100
130
ns
12
IPUL IPUH IPDH IPDL Cin
-
-
-130
A A A A pF
13
Internal Pull Up Device Current, P tested at V Min.
IH
-10
-
-
14
Internal Pull Down Device Current, P tested at V Min.
IH
-
-
130
15 16
Internal Pull Down Device Current, P tested at V Max.
IL
10
- 6
- -
D Input Capacitance
96 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted 17 Injection current3 T Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J Interrupt Input Pulse filtered4 P Port H, J Interrupt Input Pulse passed4 IICS IICP tPULSE tPULSE 10 -2.5 -25 - 2.5 25 3 mA s s
18 19
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 3. Refer to Section A.1.4 Current Injection, for more details 4. Parameter only applies in STOP or Pseudo STOP mode.
Freescale Semiconductor, Inc...
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 16MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
97 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 P
Rating
Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled, PLL on only RTI enabled 1 Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 27C 70C 85C C Temp Option 100C 105C V Temp Option 120C 125C M Temp Option 140 C Pseudo Stop Current (RTI and COP enabled) 1, 2 -40C 27C 70C 85C 105C 125C 140C Stop Current 2 -40C 27C 70C 85C C Temp Option 100C 105C V Temp Option 120C 125C M Temp Option 140C
Symbol
IDD5 IDDW
Min
Typ
Max
65 40 5
Unit
mA
2
P P C P C C P C P C P C C C C C C C C P C C P C P C P
mA
Freescale Semiconductor, Inc...
3
IDDPS
360 420 760 800 950 1000 1500 1700 2500 420 480 820 860 1050 1700 2500 20 40 200 300 550 700 1200 1400 2200
520 A
2000 3300 4800
4
IDDPS
A
100 A
5
IDDS
1500 2900 4500
NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed
98 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-8 ATD Operating Characteristics
Freescale Semiconductor, Inc...
Conditions are shown in Table A-4 unless otherwise noted
Num C
Reference Potential 1 2 3 4 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 4.50 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA
C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period D
5.00
5.25 2.0 28 14 26 13 20 0.375
Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK
5
D
NCONV8 TCONV8 tSR IREF
6 7
D Stop Recovery Time (VDDA=5.0 Volts) P Reference Supply current
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
99 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Freescale Semiconductor, Inc...
Num C
1 2 3 4 5
Rating
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 22
Unit
K pF mA A/A A/A
C Max input Source Resistance Total Input Capacitance T Non Sampling Sampling C Disruptive Analog Input Current C Coupling Ratio positive current injection C Coupling Ratio negative current injection
-2.5
2.5 10-4 10-2
100 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 A.2.3 ATD accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz Num C
1 2 3 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error1
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
5
Max
Unit
mV
-1 -2.5 -3 1.5 2.0 20 -0.5 -1.0 -1.5 0.5 1.0
1 2.5 3
Counts Counts Counts mV
Freescale Semiconductor, Inc...
4 5 6 7 8
0.5 1.0 1.5
Counts Counts Counts
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ----------------------- - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n
INL ( n ) =
i=1
Vn - V0 DNL ( i ) = ------------------- - n 1LSB
101 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
Freescale Semiconductor, Inc...
$3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 45
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-1 ATD Accuracy Definitions
NOTE:
Figure A-1 shows only definitions, for specification values refer to Table A-10.
102 For More Information On This Product, Go to: www.freescale.com
8-Bit Resolution
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.3 NVM, Flash and EEPROM
NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured.
Freescale Semiconductor, Inc...
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus
A.3.1.2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 t bwpgm
Burst programming is more than 2 times faster than single word programming.
103 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
A.3.1.3 Sector Erase
Semiconductor, Inc.
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
1 t era 4000 --------------------f NVMOP
The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes:
1 t mass 20000 --------------------f NVMOP
The setup time can be ignored for this operation.
Freescale Semiconductor, Inc...
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8
Rating
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass
Min
0.5 1 150 46 2 20.4 2 678.4 2 20 5 100 5
Typ
Max
32 1
Unit
MHz MHz
D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word 4 D Flash Burst Programming Time for 32 Words 4 P Sector Erase Time P Mass Erase Time
200 74.5 3 31 3 1035.5 3 26.7 3 133 3
kHz s s s ms ms
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. urst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures.
104 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Cycles
10 10,000
Data Retention Lifetime
15 5
Unit
Years Years
C Flash/EEPROM (-40C to +125C) C EEPROM (-40C to +125C)
Freescale Semiconductor, Inc...
NOTE: NOTE:
Flash cycling performance is 10 cycles at -40C to +125C. Data retention is specified for 15 years. EEPROM cycling performance is 10K cycles at -40C to 125C. Data retention is specified for 5 years on words after cycling 10K times. However if only 10 cycles are executed on a word the data retention is specified for 15 years.
105 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
106 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.4.1 Startup
Table A-13 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-13 Startup Characteristics
Freescale Semiconductor, Inc...
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 T POR release level T POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
Min
Typ
Max
2.07
Unit
V V tosc
0.97 2 192 20 14 196
D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time
nosc ns tcyc
A.4.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.4.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.4.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
107 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
A.4.1.4 Stop Recovery
Semiconductor, Inc.
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. A.4.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.4.2 Oscillator
Freescale Semiconductor, Inc...
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table A-14 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Rating
Symbol
fOSC iOSC nUPOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN CIN VDCBIAS
Min
0.5 100 4100
Typ
Max
16
Unit
MHz A cycOSC
C Crystal oscillator range P Startup Current D Oscillator start-up time from POR or STOP C Oscillator start-up time D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency3 D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance EXTAL pin D Input Capacitance XTAL pin C DC Operating Bias in Colpitts Configuration on EXTAL Pin
81 0.45 50 0.5 15 15 100
1002 2.5 200 32
ms s KHz MHz ns ns
1 1 9 13 1.1
ns ns pF pF V
NOTES: 1. fosc = 4MHz, C = 22pF. 2. Maximum value is for extreme cases using high Q, low frequency crystals
108 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
3. XCLKS =1 during reset
A.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.4.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL
Freescale Semiconductor, Inc...
Cs R Phase fosc 1 refdv+1 fref fcmp K Detector Loop Divider 1 synr+1
Cp
VCO KV fvco
1 2
Figure A-2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-15. The VCO Gain at the desired VCO output frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V
KV = K1 e
The phase detector relationship is given by:
K = i ch K V
ich is the current in tracking mode.
109 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- f C < ------------- ;( = 0.9 ) 4 50 50 2 + 1 +
And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
Freescale Semiconductor, Inc...
With the above inputs the resistance can be calculated as:
2 n fC R = ---------------------------K
The capacitance Cs can now be calculated as:
0.516 2 C s = --------------------- -------------- ;( = 0.9 ) fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external component selection (e.g. crystal, XFC filter). A.4.3.2 Jitter Information The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
110 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
Freescale Semiconductor, Inc...
Figure A-3 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t max ( N ) t min ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
J(N)
1
5
10
20
N
Figure A-4 Maximum bus clock jitter approximation
111 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
Table A-15 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 32 4 1.5 2.5 8
Unit
MHz MHz %1 %1 %1 %1 ms ms ms
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
Freescale Semiconductor, Inc...
D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay 2 D PLLON Tracking mode stabilization delay 2 P Fitting parameter VCO loop gain3 D Fitting parameter VCO loop frequency P Charge pump current acquisition mode P Charge pump current tracking mode C Jitter fit parameter 12 C Jitter fit parameter 22
0.5 0.3 0.2 -120 75 20 2 38.5 3.5 60 6 1.1 0.13 -224
MHz/V MHz A A % %
NOTES: 1. % deviation from target frequency 2. fREF = 4MHz, fBUS = 16MHz equivalent fVCO = 32MHz: REFDV = #$03, SYNR = #$0F, Cs = 4.7nF, Cp = 470pF, Rs = 10K. 3. K1 is measured with VXFC = 1.4V and VXFC = 1.7V @ VDD5 = 5.25V
112 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.5 MSCAN
Table A-16 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Symbol
tWUP tWUP
Min
Typ
Max
2
Unit
s s
P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass
5
Freescale Semiconductor, Inc...
113 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
114 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.6 SPI
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT)
1. If configured as output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
11
3
12
Freescale Semiconductor, Inc...
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 10
Figure A-5 SPI Master Timing (CPHA = 0)
115 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1. If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Semiconductor, Inc.
12
11
3
4
11
12
6 MSB IN2 BIT 6 . . . 1 10 LSB IN
Freescale Semiconductor, Inc...
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-6 SPI Master Timing (CPHA =1) Table A-17 SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
1 1 2 3 4 5 6 9 10 11 12 P Operating Frequency
Rating
Symbol
fop tsck tlead tlag twsck tsu thi tv tho tr tf
Min
DC 4 1/2 1/2 tbus - 30 25 0
Typ
Max
1/4 2048 --
Unit
fbus tbus tsck tsck
P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
1024 tbus
ns ns ns
25 0 25 25
ns ns ns ns
NOTES: 1. The numbers 7, 8 in the column labeled "Num" are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A-18.
116 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18 A.6.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 7 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 4 4 11 12 8 10 10 12 11 3
Freescale Semiconductor, Inc...
MISO (OUTPUT)
SLAVE 5
SLAVE LSB OUT
MOSI (INPUT)
Figure A-7 SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 11 3
10 BIT 6 . . . 1 SLAVE LSB OUT
8
Figure A-8 SPI Slave Timing (CPHA =1)
117 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table A-18 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
1 1 2 3 4 5 P Operating Frequency
Rating
Symbol
fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf
Min
DC 4 1 1 tcyc - 30 25 25
Typ
Max
1/4 2048
Unit
fbus tbus tcyc tcyc ns ns ns
P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
Freescale Semiconductor, Inc...
6 7 8 9 10 11 12
1 1 25 0 25 25
tcyc tcyc ns ns ns ns
118 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.7 LCD_32F4B
Table A.7-19 LCD_32F4B Driver Electrical Characteristics
Characteristic
LCD Supply Voltage LCD Output Impedance(BP[3:0],FP[31:0]) for outputs to charge to higher voltage level or to GND 1 LCD Output Current (BP[3:0],FP[31:0]) for outputs to discharge to lower voltage level except GND 2
Symbol
VLCD ZBP/FP
Min.
-0.25 -
Typ.
-
Max.
VDDX + 0.25 5.0
Unit
V kOhm
IBP/FP
50
-
-
uA
NOTES: 1. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin. 2. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
Freescale Semiconductor, Inc...
119 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
120 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-20. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
Freescale Semiconductor, Inc...
121 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
1, 2
3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 16
4
10 data
11
14 data
13
Freescale Semiconductor, Inc...
17 Non-Multiplexed Addresses PK5:0 20 ECS PK7
18
19
21
22
23
24 R/W PE2
25
26
27 LSTRB PE3
28
29
30 NOACC PE7
31
32
33 IPIPO0 IPIPO1, PE6,5
34
35
36
Figure A-9 General External Bus Timing
122 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
1 2 3 4 5 6 7
Rating
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
Min
0 62.5 30 30
Typ
Max
16.0
Unit
MHz ns ns ns
P Frequency of operation (E-clock) P Cycle time D Pulse width, E low D Pulse width, E high1 D Address delay time D Address valid time to E rise (PWEL-tAD) D Muxed address hold time D Address hold to data valid D Data hold to address D Read data setup time D Read data hold time D Write data delay time D Write data hold time D Write data setup time1 (PWEH-tDDW) D Address access time1 (tcyc-tAD-tDSR) D E high access time1 (PWEH-tDSR) D Non-multiplexed address delay time D Non-muxed address valid to E rise (PWEL-tNAD) D Non-multiplexed address hold time D Chip select delay time D Chip select access time1 (tcyc-tCSD-tDSR) D Chip select hold time D Chip select negated time D Read/write delay time D Read/write valid time to E rise (PWEL-tRWD) D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PWEL-tLSD) D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PWEL-tNOD)
8 22 2 7 2 24 0 7 2 23 30 6 6 26 2 6 + tcyc/4 tcyc/4 - 2 2 8 7 25 2 7 25 2 7 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Freescale Semiconductor, Inc...
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
123 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
32 33 34 35 36 D NOACC hold time D IPIPO[1:0] delay time
Rating
Symbol
tNOH tP0D tP0V tP1D tP1V
Min
2 2 22 2 22
Typ
Max
Unit
ns
7
ns ns
D IPIPO[1:0] valid time to E rise (PWEL-tP0D) D IPIPO[1:0] delay time1 (PWEH-tP1V) D IPIPO[1:0] valid time to E fall
25
ns ns
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
Freescale Semiconductor, Inc...
124 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12H256 and MC9S12H128 packages.
Freescale Semiconductor, Inc...
125 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
B.2 112-pin LQFP package
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
Freescale Semiconductor, Inc...
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)
126 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
B.3 144-pin LQFP package
4X
0.20 T L-M N
4X 36 TIPS
0.20 T L-M N
PIN 1 IDENT 1
144
109
108
J1 J1 L M B V
140X
4X
P
C L X X=L, M OR N G
Freescale Semiconductor, Inc...
VIEW Y
36 73
B1
V1
VIEW Y
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35.
37
72
N A1 S1 A S
VIEW AB C 2 2 T 0.1 T
144X MILLIMETERS DIM MIN MAX A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 0 1 0 7 2 11 13
SEATING PLANE
PLATING
J
F
AA
C2 0.05 R2 R1
D 0.08
M
BASE METAL
0.25
GAGE PLANE
T L-M N (K) C1 (Y) VIEW AB (Z) E 1
SECTION J1-J1 (ROTATED 90 )
144 PL
CASE 918-03 ISSUE C
Figure B-2 144-pin LQFP mechanical dimensions (case no. 918-03)
127 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
128 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12H256 Device User Guide -- V01.18
User Guide End Sheet
Freescale Semiconductor, Inc...
129 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12H256 Device User Guide -- V01.18
Semiconductor, Inc.
Freescale Semiconductor, Inc...
FINAL PAGE OF 130 PAGES
130 For More Information On This Product, Go to: www.freescale.com

▲Up To Search▲

Price & Availability of MC9S12H128

	To Download MC9S12H128 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .